A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping

Arindam Sanyal; Kareem Ragab; Long Chen; T. R. Viswanathan; Shouli Yan; Nan Sun

doi:10.1109/CICC.2014.6946082

A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping

Arindam Sanyal, Kareem Ragab, Long Chen, T. R. Viswanathan, Shouli Yan, Nan Sun

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

27 Scopus citations

Abstract

A scaling-friendly, hybrid, two-stage ΔΣ ADC with a 5-bit SAR as first stage and a VCO as second stage is presented in this work. Since the VCO can provide fine quantization for small signals in the time-domain, it is used to directly quantize the SAR residue without OTA-based residue amplification. Also, having a small input swing obviates the need for VCO non-linearity calibration. The VCO phase overflow problem is solved by using a counter to record the number of overflows, thus allowing a variable sampling rate. Since the VCO phase and counter are never reset, the VCO's first-order noise-shaping capability is retained. A prototype ADC in an 180 nm process achieves 73 dB SNDR over 2.2 MHz bandwidth and consumes 5 mW from a 1.8V supply while sampling at 35 MHz.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479932863
DOIs	https://doi.org/10.1109/CICC.2014.6946082
State	Published - Nov 4 2014
Externally published	Yes
Event	36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 - San Jose, United States Duration: Sep 15 2014 → Sep 17 2014

Publication series

Name	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

Other

Other	36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014
Country/Territory	United States
City	San Jose
Period	9/15/14 → 9/17/14

Keywords

analog to digital converters (ADC)
noise shaping
successive approximation register (SAR)
two stage ADC
voltage controlled oscillator (VCO)

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2014.6946082

Cite this

Sanyal, A., Ragab, K., Chen, L., Viswanathan, T. R., Yan, S., & Sun, N. (2014). A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014 Article 6946082 (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2014.6946082

A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping. / Sanyal, Arindam; Ragab, Kareem; Chen, Long et al.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6946082 (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sanyal, A, Ragab, K, Chen, L, Viswanathan, TR, Yan, S & Sun, N 2014, A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping. in Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014., 6946082, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, Institute of Electrical and Electronics Engineers Inc., 36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014, San Jose, United States, 9/15/14. https://doi.org/10.1109/CICC.2014.6946082

Sanyal A, Ragab K, Chen L, Viswanathan TR, Yan S, Sun N. A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6946082. (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014). doi: 10.1109/CICC.2014.6946082

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abstract = "A scaling-friendly, hybrid, two-stage ΔΣ ADC with a 5-bit SAR as first stage and a VCO as second stage is presented in this work. Since the VCO can provide fine quantization for small signals in the time-domain, it is used to directly quantize the SAR residue without OTA-based residue amplification. Also, having a small input swing obviates the need for VCO non-linearity calibration. The VCO phase overflow problem is solved by using a counter to record the number of overflows, thus allowing a variable sampling rate. Since the VCO phase and counter are never reset, the VCO's first-order noise-shaping capability is retained. A prototype ADC in an 180 nm process achieves 73 dB SNDR over 2.2 MHz bandwidth and consumes 5 mW from a 1.8V supply while sampling at 35 MHz.",

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N2 - A scaling-friendly, hybrid, two-stage ΔΣ ADC with a 5-bit SAR as first stage and a VCO as second stage is presented in this work. Since the VCO can provide fine quantization for small signals in the time-domain, it is used to directly quantize the SAR residue without OTA-based residue amplification. Also, having a small input swing obviates the need for VCO non-linearity calibration. The VCO phase overflow problem is solved by using a counter to record the number of overflows, thus allowing a variable sampling rate. Since the VCO phase and counter are never reset, the VCO's first-order noise-shaping capability is retained. A prototype ADC in an 180 nm process achieves 73 dB SNDR over 2.2 MHz bandwidth and consumes 5 mW from a 1.8V supply while sampling at 35 MHz.

AB - A scaling-friendly, hybrid, two-stage ΔΣ ADC with a 5-bit SAR as first stage and a VCO as second stage is presented in this work. Since the VCO can provide fine quantization for small signals in the time-domain, it is used to directly quantize the SAR residue without OTA-based residue amplification. Also, having a small input swing obviates the need for VCO non-linearity calibration. The VCO phase overflow problem is solved by using a counter to record the number of overflows, thus allowing a variable sampling rate. Since the VCO phase and counter are never reset, the VCO's first-order noise-shaping capability is retained. A prototype ADC in an 180 nm process achieves 73 dB SNDR over 2.2 MHz bandwidth and consumes 5 mW from a 1.8V supply while sampling at 35 MHz.

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A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping

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Keywords

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