A holistic approach to Network-on-Chip synthesis

Glenn Leary, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor System-on-Chip architectures. Synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints.

Original languageEnglish (US)
Title of host publication2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010
Pages213-222
Number of pages10
StatePublished - 2010
Event8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2010 - Scottsdale, AZ, United States
Duration: Oct 24 2010Oct 29 2010

Other

Other8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2010
CountryUnited States
CityScottsdale, AZ
Period10/24/1010/29/10

Fingerprint

Routers
Bandwidth
Communication
Jitter
Telecommunication traffic
Electric power utilization
Network-on-chip

Keywords

  • Best Effort
  • Deadlock Avoidance
  • Multiple Use-Cases
  • Network-on-Chip
  • Port Arity
  • Synthesis

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Leary, G., & Chatha, K. S. (2010). A holistic approach to Network-on-Chip synthesis. In 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010 (pp. 213-222). [5751504]

A holistic approach to Network-on-Chip synthesis. / Leary, Glenn; Chatha, Karam S.

2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010. 2010. p. 213-222 5751504.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Leary, G & Chatha, KS 2010, A holistic approach to Network-on-Chip synthesis. in 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010., 5751504, pp. 213-222, 8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2010, Scottsdale, AZ, United States, 10/24/10.
Leary G, Chatha KS. A holistic approach to Network-on-Chip synthesis. In 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010. 2010. p. 213-222. 5751504
Leary, Glenn ; Chatha, Karam S. / A holistic approach to Network-on-Chip synthesis. 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010. 2010. pp. 213-222
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