A holistic approach to network-on-chip synthesis

Glenn Leary, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor System-on-Chip architectures. Synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints.

Original languageEnglish (US)
Title of host publicationEmbedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010
Pages213-222
Number of pages10
DOIs
StatePublished - 2010
Event6th Embedded Systems Week, ESWEEK 2010 - 8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS'10 - Scottsdale, AZ, United States
Duration: Oct 24 2010Oct 29 2010

Other

Other6th Embedded Systems Week, ESWEEK 2010 - 8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS'10
CountryUnited States
CityScottsdale, AZ
Period10/24/1010/29/10

Fingerprint

Routers
Bandwidth
Communication
Jitter
Telecommunication traffic
Electric power utilization
Network-on-chip

Keywords

  • Best Effort
  • Deadlock avoidance
  • Multiple use-cases
  • Network-on-chip
  • Port arity
  • Synthesis

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Leary, G., & Chatha, K. S. (2010). A holistic approach to network-on-chip synthesis. In Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010 (pp. 213-222) https://doi.org/10.1145/1878961.1879001

A holistic approach to network-on-chip synthesis. / Leary, Glenn; Chatha, Karam S.

Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010. 2010. p. 213-222.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Leary, G & Chatha, KS 2010, A holistic approach to network-on-chip synthesis. in Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010. pp. 213-222, 6th Embedded Systems Week, ESWEEK 2010 - 8th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS'10, Scottsdale, AZ, United States, 10/24/10. https://doi.org/10.1145/1878961.1879001
Leary G, Chatha KS. A holistic approach to network-on-chip synthesis. In Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010. 2010. p. 213-222 https://doi.org/10.1145/1878961.1879001
Leary, Glenn ; Chatha, Karam S. / A holistic approach to network-on-chip synthesis. Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010. 2010. pp. 213-222
@inproceedings{52bdb69cf099402591692ed5d6db9834,
title = "A holistic approach to network-on-chip synthesis",
abstract = "Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor System-on-Chip architectures. Synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints.",
keywords = "Best Effort, Deadlock avoidance, Multiple use-cases, Network-on-chip, Port arity, Synthesis",
author = "Glenn Leary and Chatha, {Karam S.}",
year = "2010",
doi = "10.1145/1878961.1879001",
language = "English (US)",
isbn = "9781605589053",
pages = "213--222",
booktitle = "Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010",

}

TY - GEN

T1 - A holistic approach to network-on-chip synthesis

AU - Leary, Glenn

AU - Chatha, Karam S.

PY - 2010

Y1 - 2010

N2 - Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor System-on-Chip architectures. Synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints.

AB - Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor System-on-Chip architectures. Synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints.

KW - Best Effort

KW - Deadlock avoidance

KW - Multiple use-cases

KW - Network-on-chip

KW - Port arity

KW - Synthesis

UR - http://www.scopus.com/inward/record.url?scp=78650660964&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78650660964&partnerID=8YFLogxK

U2 - 10.1145/1878961.1879001

DO - 10.1145/1878961.1879001

M3 - Conference contribution

AN - SCOPUS:78650660964

SN - 9781605589053

SP - 213

EP - 222

BT - Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010

ER -