A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits

L. T. Clark; D. Zhao; T. Bakhishev; H. Ahn; E. Boling; M. Duane; K. Fujita; P. Gregory; T. Hoffmann; M. Hori; D. Kanai; D. Kidd; S. Lee; Y. Liu; J. Mitani; J. Nagayama; S. Pradhan; P. Ranade; R. Rogenmoser; L. Scudder; L. Shifren; Y. Torii; M. Wojko; Y. Asada; T. Ema; S. Thompson

doi:10.1109/IEDM.2012.6479042

A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits

L. T. Clark, D. Zhao, T. Bakhishev, H. Ahn, E. Boling, M. Duane, K. Fujita, P. Gregory, T. Hoffmann, M. Hori, D. Kanai, D. Kidd, S. Lee, Y. Liu, J. Mitani, J. Nagayama, S. Pradhan, P. Ranade, R. Rogenmoser, L. ScudderL. Shifren, Y. Torii, M. Wojko, Y. Asada, T. Ema, S. Thompson

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Scopus citations

Abstract

65nm Deeply Depleted Channel (DDC^TM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (V_T) variation, lower supply voltage (V _CC), enhanced body effect and I_EFF. Digital circuits made using this technology show benefits ranging from 47% power reduction to 38% frequency increase. Analog circuits exhibit 4x greater amplifier gain despite lower V_DD, and current mirror mismatch (both global and local) shows 40% and 30% reduction for NMOS and PMOS, respectively.

Original language	English (US)
Title of host publication	2012 IEEE International Electron Devices Meeting, IEDM 2012
Pages	14.4.1-14.4.4
DOIs	https://doi.org/10.1109/IEDM.2012.6479042
State	Published - 2012
Externally published	Yes
Event	2012 IEEE International Electron Devices Meeting, IEDM 2012 - San Francisco, CA, United States Duration: Dec 10 2012 → Dec 13 2012

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Other

Other	2012 IEEE International Electron Devices Meeting, IEDM 2012
Country/Territory	United States
City	San Francisco, CA
Period	12/10/12 → 12/13/12

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1109/IEDM.2012.6479042

Cite this

Clark, L. T., Zhao, D., Bakhishev, T., Ahn, H., Boling, E., Duane, M., Fujita, K., Gregory, P., Hoffmann, T., Hori, M., Kanai, D., Kidd, D., Lee, S., Liu, Y., Mitani, J., Nagayama, J., Pradhan, S., Ranade, P., Rogenmoser, R., ... Thompson, S. (2012). A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits. In 2012 IEEE International Electron Devices Meeting, IEDM 2012 (pp. 14.4.1-14.4.4). [6479042] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2012.6479042

A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits. / Clark, L. T.; Zhao, D.; Bakhishev, T. et al.

2012 IEEE International Electron Devices Meeting, IEDM 2012. 2012. p. 14.4.1-14.4.4 6479042 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Clark, LT, Zhao, D, Bakhishev, T, Ahn, H, Boling, E, Duane, M, Fujita, K, Gregory, P, Hoffmann, T, Hori, M, Kanai, D, Kidd, D, Lee, S, Liu, Y, Mitani, J, Nagayama, J, Pradhan, S, Ranade, P, Rogenmoser, R, Scudder, L, Shifren, L, Torii, Y, Wojko, M, Asada, Y, Ema, T & Thompson, S 2012, A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits. in 2012 IEEE International Electron Devices Meeting, IEDM 2012., 6479042, Technical Digest - International Electron Devices Meeting, IEDM, pp. 14.4.1-14.4.4, 2012 IEEE International Electron Devices Meeting, IEDM 2012, San Francisco, CA, United States, 12/10/12. https://doi.org/10.1109/IEDM.2012.6479042

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abstract = "65nm Deeply Depleted Channel (DDCTM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (VT) variation, lower supply voltage (V CC), enhanced body effect and IEFF. Digital circuits made using this technology show benefits ranging from 47% power reduction to 38% frequency increase. Analog circuits exhibit 4x greater amplifier gain despite lower VDD, and current mirror mismatch (both global and local) shows 40% and 30% reduction for NMOS and PMOS, respectively.",

author = "Clark, {L. T.} and D. Zhao and T. Bakhishev and H. Ahn and E. Boling and M. Duane and K. Fujita and P. Gregory and T. Hoffmann and M. Hori and D. Kanai and D. Kidd and S. Lee and Y. Liu and J. Mitani and J. Nagayama and S. Pradhan and P. Ranade and R. Rogenmoser and L. Scudder and L. Shifren and Y. Torii and M. Wojko and Y. Asada and T. Ema and S. Thompson",

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AU - Duane, M.

AU - Fujita, K.

AU - Gregory, P.

AU - Hoffmann, T.

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AU - Kanai, D.

AU - Kidd, D.

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AU - Liu, Y.

AU - Mitani, J.

AU - Nagayama, J.

AU - Pradhan, S.

AU - Ranade, P.

AU - Rogenmoser, R.

AU - Scudder, L.

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AU - Asada, Y.

AU - Ema, T.

AU - Thompson, S.

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AB - 65nm Deeply Depleted Channel (DDCTM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (VT) variation, lower supply voltage (V CC), enhanced body effect and IEFF. Digital circuits made using this technology show benefits ranging from 47% power reduction to 38% frequency increase. Analog circuits exhibit 4x greater amplifier gain despite lower VDD, and current mirror mismatch (both global and local) shows 40% and 30% reduction for NMOS and PMOS, respectively.

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A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits

Abstract

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ASJC Scopus subject areas

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