A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits

L. T. Clark, D. Zhao, T. Bakhishev, H. Ahn, E. Boling, M. Duane, K. Fujita, P. Gregory, T. Hoffmann, M. Hori, D. Kanai, D. Kidd, S. Lee, Y. Liu, J. Mitani, J. Nagayama, S. Pradhan, P. Ranade, R. Rogenmoser, L. ScudderL. Shifren, Y. Torii, M. Wojko, Y. Asada, T. Ema, S. Thompson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

65nm Deeply Depleted Channel (DDCTM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (VT) variation, lower supply voltage (V CC), enhanced body effect and IEFF. Digital circuits made using this technology show benefits ranging from 47% power reduction to 38% frequency increase. Analog circuits exhibit 4x greater amplifier gain despite lower VDD, and current mirror mismatch (both global and local) shows 40% and 30% reduction for NMOS and PMOS, respectively.

Original languageEnglish (US)
Title of host publication2012 IEEE International Electron Devices Meeting, IEDM 2012
Pages14.4.1-14.4.4
DOIs
StatePublished - 2012
Event2012 IEEE International Electron Devices Meeting, IEDM 2012 - San Francisco, CA, United States
Duration: Dec 10 2012Dec 13 2012

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2012 IEEE International Electron Devices Meeting, IEDM 2012
CountryUnited States
CitySan Francisco, CA
Period12/10/1212/13/12

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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