A highly digital second-order oversampling TDC

Sanjeev Tannirkulam Chandrasekaran, Akshay Jayaraj, Mohammadhadi Danesh, Arindam Sanyal

Research output: Contribution to journalArticlepeer-review

10 Scopus citations

Abstract

A second-order, single loop Δ Σ time-to-digital converter (TDC) is presented in this letter. The proposed TDC uses two differential current-controlled oscillators as phase domain integrators. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Digital differentiation using XOR implements an intrinsic first-order high-pass shaping of static element mismatch in the current steering digital-to-analog converter. A prototype TDC in 65-nm CMOS process has linearity of 8.1 bits, integrated noise of 3.8 ps and energy efficiency of 0.45 pJ/code over a bandwidth of 2.5 MHz.

Original languageEnglish (US)
Article number8490720
Pages (from-to)114-117
Number of pages4
JournalIEEE Solid-State Circuits Letters
Volume1
Issue number5
DOIs
StatePublished - May 2018
Externally publishedYes

Keywords

  • Current-controlled oscillator
  • Delta-sigma
  • Noise shaping
  • Time-to-digital converter

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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