Abstract
JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination required in the present wireless and internet age. These features are possible due to adaptation of discrete wavelet transform, intra-subband bit plane coding and binary arithmetic coding. All the three algorithms are complex and require substantial number of memory accesses. In this paper we propose a system level architecture capable of encoding and decoding using the JPEG2000 core algorithm. The key components include dedicated architectures for wavelet, bit plane and arithmetic coders and memory interfacing between the coders. The system architecture has been implemented in VHDL and its performance evaluated for a set of images. The estimated area of the architecture, in 0.18 μ technology, is 3 mm square and the estimated frequency of operation is 200 Mhz.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 1 |
| State | Published - 2002 |
| Event | 2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States Duration: May 26 2002 → May 29 2002 |
Other
| Other | 2002 IEEE International Symposium on Circuits and Systems |
|---|---|
| Country | United States |
| City | Phoenix, AZ |
| Period | 5/26/02 → 5/29/02 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
A high performance JPEG2000 architecture. / Andra, Kishore; Chakrabarti, Chaitali; Acharya, Tinku.
Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 1 2002.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A high performance JPEG2000 architecture
AU - Andra, Kishore
AU - Chakrabarti, Chaitali
AU - Acharya, Tinku
PY - 2002
Y1 - 2002
N2 - JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination required in the present wireless and internet age. These features are possible due to adaptation of discrete wavelet transform, intra-subband bit plane coding and binary arithmetic coding. All the three algorithms are complex and require substantial number of memory accesses. In this paper we propose a system level architecture capable of encoding and decoding using the JPEG2000 core algorithm. The key components include dedicated architectures for wavelet, bit plane and arithmetic coders and memory interfacing between the coders. The system architecture has been implemented in VHDL and its performance evaluated for a set of images. The estimated area of the architecture, in 0.18 μ technology, is 3 mm square and the estimated frequency of operation is 200 Mhz.
AB - JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination required in the present wireless and internet age. These features are possible due to adaptation of discrete wavelet transform, intra-subband bit plane coding and binary arithmetic coding. All the three algorithms are complex and require substantial number of memory accesses. In this paper we propose a system level architecture capable of encoding and decoding using the JPEG2000 core algorithm. The key components include dedicated architectures for wavelet, bit plane and arithmetic coders and memory interfacing between the coders. The system architecture has been implemented in VHDL and its performance evaluated for a set of images. The estimated area of the architecture, in 0.18 μ technology, is 3 mm square and the estimated frequency of operation is 200 Mhz.
UR - http://www.scopus.com/inward/record.url?scp=0036292506&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0036292506&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0036292506
VL - 1
BT - Proceedings - IEEE International Symposium on Circuits and Systems
ER -