A high performance JPEG2000 architecture

Kishore Andra, Chaitali Chakrabarti, Tinku Acharya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination required in the present wireless and internet age. These features are possible due to adaptation of discrete wavelet transform, intra-subband bit plane coding and binary arithmetic coding. All the three algorithms are complex and require substantial number of memory accesses. In this paper we propose a system level architecture capable of encoding and decoding using the JPEG2000 core algorithm. The key components include dedicated architectures for wavelet, bit plane and arithmetic coders and memory interfacing between the coders. The system architecture has been implemented in VHDL and its performance evaluated for a set of images. The estimated area of the architecture, in 0.18 μ technology, is 3 mm square and the estimated frequency of operation is 200 Mhz.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Volume1
StatePublished - 2002
Event2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States
Duration: May 26 2002May 29 2002

Other

Other2002 IEEE International Symposium on Circuits and Systems
CountryUnited States
CityPhoenix, AZ
Period5/26/025/29/02

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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    Andra, K., Chakrabarti, C., & Acharya, T. (2002). A high performance JPEG2000 architecture. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 1)