Abstract
This paper presents a high IIP3 9.9 GHz down-conversion mixer design with bandwidth of 1.2 GHz for radar systems. It is a Gilbert-cell mixer integrated in an IBM SiGe BiC-MOS 7HP process. MOS transistors are used for RF stage to improve the linearity of the mixer. Bipolar transistors are used as the LO stage for their good switching performance. Both input and output are matched to 50 Ω. The LO frequency is at 6 GHz. At IF output, two LC matching stages are cascaded for a wide band output impedance matching. A simulation-based synthesis tool is used for optimization of this mixer. The designed mixer requires a 2.5 V supply voltage and consumes 35 mW DC power. At the frequency range of 9.3 - 10.5 GHz, this mixer has single-sideband noise figure (SSB NF) less than 10.8 dB, with input and output return loss less than -12.5 dB and -11.5 dB respectively, third-order input intercept point (IIP3) of 17.8 dBm, and conversion gain above 0 dB.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 1 |
| State | Published - 2004 |
| Event | 2004 IEEE International Symposium on Circuits and Systems - Proceedings - Vancouver, BC, Canada Duration: May 23 2004 → May 26 2004 |
Other
| Other | 2004 IEEE International Symposium on Circuits and Systems - Proceedings |
|---|---|
| Country/Territory | Canada |
| City | Vancouver, BC |
| Period | 5/23/04 → 5/26/04 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering