A graph drawing based spatial mapping algorithm for coarse-grained reconfigurable architectures

Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Yunheung Paek

Research output: Contribution to journalArticle

32 Citations (Scopus)

Abstract

Recently coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their efficiency and flexibility. While many CGRAs have demonstrated impressive performance improvements, the effectiveness of CGRA platforms ultimately hinges on the compiler. Existing CGRA compilers do not model the details of the CGRA, and thus they are i) unable to map applications, even though a mapping exists, and ii) using too many processing elements (PEs) to map an application. In this paper, we model several CGRA details, e.g., irregular CGRA topologies, shared resources and routing PEs in our compiler and develop a graph drawing based approach, Split-Push Kernel Mapping (SPKM), for mapping applications onto CGRAs. On randomly generated graphs our technique can map on average 4.5$\times$ more applications than the previous approach, while generating mappings which have better qualities in terms of utilized CGRA resources. Utilizing fewer resources is directly translated into increased opportunities for novel power and performance optimization techniques. Our technique shows less power consumption in 71 cases and shorter execution cycles in 66 cases out of 100 synthetic applications, with minimum mapping time overhead. We observe similar results on a suite of benchmarks collected from Livermore loops, Mediabench, Multimedia, Wavelet and DSPStone benchmarks. SPKM is not a customized algorithm only for a specific CGRA template, and it is demonstrated by exploring various PE interconnection topologies and shared resource configurations with SPKM.

Original languageEnglish (US)
Article number4801596
Pages (from-to)1565-1578
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume17
Issue number11
DOIs
StatePublished - Nov 2009

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Drawing (graphics)
Reconfigurable architectures
Processing
Topology
Hinges

Keywords

  • Compiler
  • Kernel mapping
  • Reconfigurable architecture

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

Cite this

A graph drawing based spatial mapping algorithm for coarse-grained reconfigurable architectures. / Yoon, Jonghee W.; Shrivastava, Aviral; Park, Sanghyun; Ahn, Minwook; Paek, Yunheung.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 11, 4801596, 11.2009, p. 1565-1578.

Research output: Contribution to journalArticle

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