A GPU-outperforming FPGA accelerator architecture for binary convolutional neural networks

Yixing Li, Zichuan Liu, Kai Xu, Hao Yu, Fengbo Ren

Research output: Contribution to journalArticle

13 Scopus citations

Abstract

FPGA-based hardware accelerators for convolutional neural networks (CNNs) have received attention due to their higher energy efficiency than GPUs. However, it is challenging for FPGA-based solutions to achieve a higher throughput than GPU counterparts. In this article, we demonstrate that FPGA acceleration can be a superior solution in terms of both throughput and energy efficiency when a CNN is trained with binary constraints on weights and activations. Specifically, we propose an optimized fully mapped FPGA accelerator architecture tailored for bitwise convolution and normalization that features massive spatial parallelism with deep pipelines stages. A key advantage of the FPGA accelerator is that its performance is insensitive to data batch size, while the performance of GPU acceleration varies largely depending on the batch size of the data. Experiment results show that the proposed accelerator architecture for binary CNNs running on a Virtex-7 FPGA is 8.3× faster and 75× more energy-efficient than a Titan X GPU for processing online individual requests in small batch sizes. For processing static data in large batch sizes, the proposed solution is on a par with a Titan X GPU in terms of throughput while delivering 9.5× higher energy efficiency.

Original languageEnglish (US)
Article number3154839
JournalACM Journal on Emerging Technologies in Computing Systems
Volume14
Issue number2
DOIs
StatePublished - Jul 2018

Keywords

  • Binary neural network
  • Convolutional neural network
  • Deep learning
  • Energy efficiency
  • FPGA
  • Hardware acceleration
  • High-throughput

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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