Abstract
A 3.3V, 0.8 mW programmable Numerical Controlled oscillator Oscillator (NCO) core is designed in 0.6 micron CMOS process and its prototype design is mapped on an Altera MAX9400 CPLD. This architecture is suitable for digital wireless transceivers that use different bands for transmit and receive modes, such as GSM and DECT. Linearity and phase noise of the NCO is analyzed. Thermal drift and power supply level sensitivity is characterized. This architecture can be used for higher frequencies using faster FPGA devices or by implementing it on an advanced deep-submicron process.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 389-398 |
| Number of pages | 10 |
| Journal | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
| Volume | 2799 |
| State | Published - 2003 |
| Externally published | Yes |
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ASJC Scopus subject areas
- Computer Science(all)
- Biochemistry, Genetics and Molecular Biology(all)
- Theoretical Computer Science
Cite this
A fully digital numerical-controlled-oscillator. / Abdollahi, S. R.; Bakkaloglu, Bertan; Hosseini, S. K.
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2799, 2003, p. 389-398.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A fully digital numerical-controlled-oscillator
AU - Abdollahi, S. R.
AU - Bakkaloglu, Bertan
AU - Hosseini, S. K.
PY - 2003
Y1 - 2003
N2 - A 3.3V, 0.8 mW programmable Numerical Controlled oscillator Oscillator (NCO) core is designed in 0.6 micron CMOS process and its prototype design is mapped on an Altera MAX9400 CPLD. This architecture is suitable for digital wireless transceivers that use different bands for transmit and receive modes, such as GSM and DECT. Linearity and phase noise of the NCO is analyzed. Thermal drift and power supply level sensitivity is characterized. This architecture can be used for higher frequencies using faster FPGA devices or by implementing it on an advanced deep-submicron process.
AB - A 3.3V, 0.8 mW programmable Numerical Controlled oscillator Oscillator (NCO) core is designed in 0.6 micron CMOS process and its prototype design is mapped on an Altera MAX9400 CPLD. This architecture is suitable for digital wireless transceivers that use different bands for transmit and receive modes, such as GSM and DECT. Linearity and phase noise of the NCO is analyzed. Thermal drift and power supply level sensitivity is characterized. This architecture can be used for higher frequencies using faster FPGA devices or by implementing it on an advanced deep-submicron process.
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UR - http://www.scopus.com/inward/citedby.url?scp=35248840960&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:35248840960
VL - 2799
SP - 389
EP - 398
JO - Lecture Notes in Computer Science
JF - Lecture Notes in Computer Science
SN - 0302-9743
ER -