Abstract
A 3.3V, 0.8 mW programmable Numerical Controlled oscillator Oscillator (NCO) core is designed in 0.6 micron CMOS process and its prototype design is mapped on an Altera MAX9400 CPLD. This architecture is suitable for digital wireless transceivers that use different bands for transmit and receive modes, such as GSM and DECT. Linearity and phase noise of the NCO is analyzed. Thermal drift and power supply level sensitivity is characterized. This architecture can be used for higher frequencies using faster FPGA devices or by implementing it on an advanced deep-submicron process.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 389-398 |
| Number of pages | 10 |
| Journal | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
| Volume | 2799 |
| State | Published - Dec 1 2003 |
| Externally published | Yes |
ASJC Scopus subject areas
- Theoretical Computer Science
- General Computer Science