A fully digital numerical-controlled-oscillator

S. R. Abdollahi, Bertan Bakkaloglu, S. K. Hosseini

Research output: Contribution to journalArticle

Abstract

A 3.3V, 0.8 mW programmable Numerical Controlled oscillator Oscillator (NCO) core is designed in 0.6 micron CMOS process and its prototype design is mapped on an Altera MAX9400 CPLD. This architecture is suitable for digital wireless transceivers that use different bands for transmit and receive modes, such as GSM and DECT. Linearity and phase noise of the NCO is analyzed. Thermal drift and power supply level sensitivity is characterized. This architecture can be used for higher frequencies using faster FPGA devices or by implementing it on an advanced deep-submicron process.

Original languageEnglish (US)
Pages (from-to)389-398
Number of pages10
JournalLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2799
StatePublished - 2003
Externally publishedYes

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Cordless telephones
Electric Power Supplies
Global system for mobile communications
Phase noise
Transceivers
Field programmable gate arrays (FPGA)
Hot Temperature
Equipment and Supplies
Phase Noise
Linearity
Field Programmable Gate Array
Prototype

ASJC Scopus subject areas

  • Computer Science(all)
  • Biochemistry, Genetics and Molecular Biology(all)
  • Theoretical Computer Science

Cite this

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