A fully-adjustable dynamic range capacitance sensing circuit in a 0.15μm 3D SOI process

Jianan Song, David Welch, Jennifer Blain Christen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

We describe a fully-adjustable dynamic range capacitance sensor circuit implemented with switched capacitors in a 3D process. The dynamic range and sampling frequency are set by the frequency of two clock inputs that control an on-chip four phase non-overlapping clock generation circuit. The chip also contains a bandgap reference, increasing the accuracy of the capacitance measurements. It also has full temperature control capabilities via the PTAT circuit and resistive heating element. The circuits were fully simulated using the Cadence IC 6 simulation tool. The 3D chips were provided by Lincoln Lab at Massachusetts Institute of Technology (MITLL). MITLL fabricate a 3D wafer by bonding 3 stacked wafers each from the IBM silicon over insulator (SOI) 0.15 m process.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages1708-1711
Number of pages4
DOIs
Publication statusPublished - 2011
Event2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil
Duration: May 15 2011May 18 2011

Other

Other2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
CountryBrazil
CityRio de Janeiro
Period5/15/115/18/11

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Song, J., Welch, D., & Blain Christen, J. (2011). A fully-adjustable dynamic range capacitance sensing circuit in a 0.15μm 3D SOI process. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1708-1711). [5937911] https://doi.org/10.1109/ISCAS.2011.5937911