A Fractional-N PLL with Space-Time Averaging for Quantization Noise Reduction

Yanlong Zhang, Arindam Sanyal, Xueyi Yu, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, Nan Sun

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

This article presents a space-time averaging technique that can realize instantaneous fractional frequency division, and thus, can significantly reduce the quantization error in a fractional- $N$ phase-locked loop (PLL). Spatial averaging can be achieved by using an array of dividers running in parallel. Their different division ratios are generated by using a fractional $\Delta \Sigma $ modulator (DSM) and a dynamic element matching (DEM) block. To reduce the divider power, this article also proposes a way to achieve spatial averaging using only one divider and phase selection. A prototype 2.4-GHz fractional- $N$ PLL is implemented in a 40-nm CMOS process. Measurement results show that the proposed technique reduces the phase noise by 10 and 21 dB at the 1- and 10-MHz offset, respectively, leading to a reduction of the integrated rms jitter from 9.55 to 2.26 ps.

Original languageEnglish (US)
Article number8896938
Pages (from-to)602-614
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Volume55
Issue number3
DOIs
StatePublished - Mar 2020
Externally publishedYes

Keywords

  • data-weighted averaging (DWA)
  • dynamic element matching (DEM)
  • fractional-N PLL
  • frequency synthesizer
  • phase noise
  • phase-locked loop (PLL)
  • quantization noise reduction
  • ΔΣ modulator (DSM)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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