A finite-point method for efficient gate characterization under multiple input switching

Anupama R. Subramaniam, Janet Roveda, Yu Cao

Research output: Contribution to journalArticle

Abstract

Timing characterization of standard cells is one of the essential steps in VLSI design. The traditional static timing analysis (STA) tool assumes single input switching models for the characterization of multiple input gates. However, due to technology scaling, increasing operating frequency, and process variation, the probability of the occurrence of multiple input switching (MIS) is increasing. On the other hand, considering all possible MIS scenarios for the characterization of multiple input logic gates, is computationally intensive. To improve the efficiency, this work proposes a finite-point-based characterization methodology for multiple input gates with the effects of MIS. Furthermore, delay variation due to MIS is integrated into the STA flow through propagation of switching windows. The proposed modeling methodology is validated using benchmark circuits at the 45nm technology node for various operating conditions. Experimental results demonstrate significant reduction in computation cost and data volume with less than ∼10% error compared to that of traditional SPICE simulation.

Original languageEnglish (US)
Article number10
JournalACM Transactions on Design Automation of Electronic Systems
Volume21
Issue number1
DOIs
StatePublished - Nov 1 2015

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Keywords

  • Characterization
  • Design flow
  • Finite point method
  • Flow
  • Logic
  • Multiple input switching
  • Performance verification
  • Standard cell characterization

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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