Abstract

We have developed a technique for fast screening of carrier generation lifetime in ultraclean silicon wafers by employing deep-level transient spectroscopy (DLTS) measurements on metal-oxide-semiconductor-capacitor (MOS-C) test structures. Results show that the screened lifetime is of sufficient accuracy to distinguish metallic impurities with densities as low as (10 10) cm (10-3) in thin p/p+ silicon epitaxial layers. The widely used classic pulsed MOS-C technique is shown to be inaccurate and unable to separate bulk and surface components of the lifetime, while its modified and more accurate versions are time consuming and unaffordable for process screening purposes.

Original languageEnglish (US)
Article number6867334
Pages (from-to)3282-3288
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume61
Issue number9
DOIs
StatePublished - Sep 2014

Keywords

  • Carrier lifetimes
  • deep-level transient spectroscopy (DLTS)
  • metal-oxide-semiconductor capacitors (MOS-C)
  • semiconductor defects
  • semiconductor device measurements
  • semiconductor materials
  • silicon

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A fast technique to screen carrier generation lifetime using DLTS on MOS capacitors'. Together they form a unique fingerprint.

  • Cite this