A fast, energy efficient, field programmable threshold-logic array

Niranjan Kulkarni, Jinghua Yang, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Threshold-logic gates have long been known to result in more compact and faster circuits when compared to conventional AND/OR logic equivalents [1], However, threshold logic based design has not entered the mainstream design technology (neither custom ASIC nor FPGA) due to the lack of efficient and reliable gate implementations and the necessary infrastructure for automated synthesis and physical design. This paper is a step toward addressing this gap. We present the architecture of a novel programmable logic array, referred to as Field Programmable Threshold-Logic Array (FPTLA), in which the basic cells are differential mode threshold-logic gates (DTGs). Each individual DTG cell is a clock edge-triggered circuit that computes a threshold-logic function. A DTG can be programmed to implement different threshold logic functions by routing appropriate signals to their inputs. This reduces the number of SRAMs inside the logic blocks by about 60% compared to conventional CLBs, without adding any significant overhead in the routing infrastructure. Since a DTG is essentially a multi-input, edge-triggered flipflop that computes a threshold function, a network of DTGs forms a nano-pipelined circuit. The advantages of such a network are demonstrated on a set of deeply pipelined datapath circuits implemented on FPTLAs and conventional FPGAs using the well established FPGA design framework VTR (Verilog To Routing) and VPR (Versatile Place and Route) [2]. The results indicate that an FPTLA can achieve up to 2X improvement in delay for nearly the same energy and logic area compared to the conventional LUT based FPGA. Although differential mode circuits can potentially be more sensitive to process variations, FPTLAs can be made robust to such variations without sacrificing their improved energy efficiency and performance over FPGAs.

Original languageEnglish (US)
Title of host publicationProceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages300-305
Number of pages6
ISBN (Print)9781479962457
DOIs
StatePublished - Apr 8 2015
Event13th International Conference on Field-Programmable Technology, FPT 2014 - Shanghai, China
Duration: Dec 10 2014Dec 12 2014

Other

Other13th International Conference on Field-Programmable Technology, FPT 2014
CountryChina
CityShanghai
Period12/10/1412/12/14

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Science Applications

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  • Cite this

    Kulkarni, N., Yang, J., & Vrudhula, S. (2015). A fast, energy efficient, field programmable threshold-logic array. In Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014 (pp. 300-305). [7082804] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPT.2014.7082804