Abstract
Considerable work has been devoted to studying flexible computation structures for the physical layer of a software defined radio (SDR) terminal. However there has been almost no research on protocol processors for the upper layer protocols such as the media access control (MAC) and link protocol. A general purpose processor (GPP) is sufficient for the protocol processing of a single mode terminal. However, in the case of a multi-mode system required for SDR, there is a very wide set of possibilities for the MAC layer. In principle these too could be handled by a GPP. However, we show that a better solution is to use a GPP augmented by a small supplemental processor. The GPP is responsible for the relatively complex protocol operations in the active mode, and the supplemental processor handles the idle mode operations. This separation of responsibilities simplifies the implementation of hard real-time responses required by some protocols (for example IEEE 802.11), while maintaining the programmability needed to handle a wide range of protocols. In addition, this organization allows a significant power savings in the idle mode. This is important because the protocol processor must process a large number of tiny idle mode tasks whose aggregate effect over time dominates the power consumption in a wireless terminal. As part of our study we develop a hardware model of the supplemental processor in Verilog and its software model in C. Using commercial CAD tools we synthesized out design and evaluated the power consumption and response time of the platform. Our results show that the proposed platform meets the real-time deadlines at low power while maintaining programmability.
| Original language | English (US) |
|---|---|
| Title of host publication | CASES 2005 |
| Subtitle of host publication | International Conference on Compilers, Architecture, and Synthesis for Embedded Systems |
| Pages | 257-265 |
| Number of pages | 9 |
| State | Published - Dec 23 2005 |
| Externally published | Yes |
| Event | CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems - San Francisco, CA, United States Duration: Sep 24 2005 → Sep 27 2005 |
Other
| Other | CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems |
|---|---|
| Country | United States |
| City | San Francisco, CA |
| Period | 9/24/05 → 9/27/05 |
Fingerprint
Keywords
- Protocol processing
- SDR terminal
- Wireless platform
ASJC Scopus subject areas
- Engineering(all)
Cite this
A dual-processor solution for the MAC layer of a software defined radio terminal. / LEE, Hyunseok; Mudge, Trevor.
CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. 2005. p. 257-265.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A dual-processor solution for the MAC layer of a software defined radio terminal
AU - LEE, Hyunseok
AU - Mudge, Trevor
PY - 2005/12/23
Y1 - 2005/12/23
N2 - Considerable work has been devoted to studying flexible computation structures for the physical layer of a software defined radio (SDR) terminal. However there has been almost no research on protocol processors for the upper layer protocols such as the media access control (MAC) and link protocol. A general purpose processor (GPP) is sufficient for the protocol processing of a single mode terminal. However, in the case of a multi-mode system required for SDR, there is a very wide set of possibilities for the MAC layer. In principle these too could be handled by a GPP. However, we show that a better solution is to use a GPP augmented by a small supplemental processor. The GPP is responsible for the relatively complex protocol operations in the active mode, and the supplemental processor handles the idle mode operations. This separation of responsibilities simplifies the implementation of hard real-time responses required by some protocols (for example IEEE 802.11), while maintaining the programmability needed to handle a wide range of protocols. In addition, this organization allows a significant power savings in the idle mode. This is important because the protocol processor must process a large number of tiny idle mode tasks whose aggregate effect over time dominates the power consumption in a wireless terminal. As part of our study we develop a hardware model of the supplemental processor in Verilog and its software model in C. Using commercial CAD tools we synthesized out design and evaluated the power consumption and response time of the platform. Our results show that the proposed platform meets the real-time deadlines at low power while maintaining programmability.
AB - Considerable work has been devoted to studying flexible computation structures for the physical layer of a software defined radio (SDR) terminal. However there has been almost no research on protocol processors for the upper layer protocols such as the media access control (MAC) and link protocol. A general purpose processor (GPP) is sufficient for the protocol processing of a single mode terminal. However, in the case of a multi-mode system required for SDR, there is a very wide set of possibilities for the MAC layer. In principle these too could be handled by a GPP. However, we show that a better solution is to use a GPP augmented by a small supplemental processor. The GPP is responsible for the relatively complex protocol operations in the active mode, and the supplemental processor handles the idle mode operations. This separation of responsibilities simplifies the implementation of hard real-time responses required by some protocols (for example IEEE 802.11), while maintaining the programmability needed to handle a wide range of protocols. In addition, this organization allows a significant power savings in the idle mode. This is important because the protocol processor must process a large number of tiny idle mode tasks whose aggregate effect over time dominates the power consumption in a wireless terminal. As part of our study we develop a hardware model of the supplemental processor in Verilog and its software model in C. Using commercial CAD tools we synthesized out design and evaluated the power consumption and response time of the platform. Our results show that the proposed platform meets the real-time deadlines at low power while maintaining programmability.
KW - Protocol processing
KW - SDR terminal
KW - Wireless platform
UR - http://www.scopus.com/inward/record.url?scp=29144471990&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=29144471990&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:29144471990
SN - 159593149X
SN - 9781595931498
SP - 257
EP - 265
BT - CASES 2005
ER -