TY - GEN
T1 - A distributed Canny edge detector and its implementation on FPGA
AU - Xu, Qian
AU - Chakrabarti, Chaitali
AU - Karam, Lina
PY - 2011
Y1 - 2011
N2 - Edge detection is one of the key stages in image processing and object recognition. The Canny edge detector is one of the most widely-used edge detection algorithms due to its good performance. In this paper, we present a distributed Canny edge detection algorithm that results in significantly reduced memory requirements, decreased latency and increased throughput with no loss in edge detection performance as compared to the original Canny algorithm. The new algorithm uses a low-complexity 8-bin non-uniform gradient magnitude histogram to compute block-based hysteresis thresholds that are used by the Canny edge detector. Furthermore, an FPGA-based hardware architecture of our proposed algorithm is presented in this paper and the architecture is synthesized on the Xilinx Virtex-5 FPGA. Simulation results are presented to illustrate the performance of the proposed distributed Canny edge detector. The FPGA simulation results show that we can process a 512512 image in 0.287ms at a clock rate of 100 MHz.
AB - Edge detection is one of the key stages in image processing and object recognition. The Canny edge detector is one of the most widely-used edge detection algorithms due to its good performance. In this paper, we present a distributed Canny edge detection algorithm that results in significantly reduced memory requirements, decreased latency and increased throughput with no loss in edge detection performance as compared to the original Canny algorithm. The new algorithm uses a low-complexity 8-bin non-uniform gradient magnitude histogram to compute block-based hysteresis thresholds that are used by the Canny edge detector. Furthermore, an FPGA-based hardware architecture of our proposed algorithm is presented in this paper and the architecture is synthesized on the Xilinx Virtex-5 FPGA. Simulation results are presented to illustrate the performance of the proposed distributed Canny edge detector. The FPGA simulation results show that we can process a 512512 image in 0.287ms at a clock rate of 100 MHz.
KW - Canny Edge detector
KW - Distributed Processing
KW - FPGA
KW - Non-uniform quantization
UR - http://www.scopus.com/inward/record.url?scp=79954547604&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79954547604&partnerID=8YFLogxK
U2 - 10.1109/DSP-SPE.2011.5739265
DO - 10.1109/DSP-SPE.2011.5739265
M3 - Conference contribution
AN - SCOPUS:79954547604
SN - 9781612842271
T3 - 2011 Digital Signal Processing and Signal Processing Education Meeting, DSP/SPE 2011 - Proceedings
SP - 500
EP - 505
BT - 2011 Digital Signal Processing and Signal Processing Education Meeting, DSP/SPE 2011 - Proceedings
T2 - 2011 Digital Signal Processing and Signal Processing Education Meeting, DSP/SPE 2011
Y2 - 4 January 2011 through 7 January 2011
ER -