22 Citations (Scopus)

Abstract

Edge detection is one of the key stages in image processing and object recognition. The Canny edge detector is one of the most widely-used edge detection algorithms due to its good performance. In this paper, we present a distributed Canny edge detection algorithm that results in significantly reduced memory requirements, decreased latency and increased throughput with no loss in edge detection performance as compared to the original Canny algorithm. The new algorithm uses a low-complexity 8-bin non-uniform gradient magnitude histogram to compute block-based hysteresis thresholds that are used by the Canny edge detector. Furthermore, an FPGA-based hardware architecture of our proposed algorithm is presented in this paper and the architecture is synthesized on the Xilinx Virtex-5 FPGA. Simulation results are presented to illustrate the performance of the proposed distributed Canny edge detector. The FPGA simulation results show that we can process a 512512 image in 0.287ms at a clock rate of 100 MHz.

Original languageEnglish (US)
Title of host publication2011 Digital Signal Processing and Signal Processing Education Meeting, DSP/SPE 2011 - Proceedings
Pages500-505
Number of pages6
DOIs
StatePublished - 2011
Event2011 Digital Signal Processing and Signal Processing Education Meeting, DSP/SPE 2011 - Sedona, AZ, United States
Duration: Jan 4 2011Jan 7 2011

Other

Other2011 Digital Signal Processing and Signal Processing Education Meeting, DSP/SPE 2011
CountryUnited States
CitySedona, AZ
Period1/4/111/7/11

Fingerprint

Field programmable gate arrays (FPGA)
Edge detection
Detectors
performance
hysteresis
simulation
Object recognition
Bins
hardware
Hysteresis
Clocks
Image processing
Throughput
Hardware
Data storage equipment

Keywords

  • Canny Edge detector
  • Distributed Processing
  • FPGA
  • Non-uniform quantization

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Signal Processing
  • Education

Cite this

Xu, Q., Chakrabarti, C., & Karam, L. (2011). A distributed Canny edge detector and its implementation on FPGA. In 2011 Digital Signal Processing and Signal Processing Education Meeting, DSP/SPE 2011 - Proceedings (pp. 500-505). [5739265] https://doi.org/10.1109/DSP-SPE.2011.5739265

A distributed Canny edge detector and its implementation on FPGA. / Xu, Qian; Chakrabarti, Chaitali; Karam, Lina.

2011 Digital Signal Processing and Signal Processing Education Meeting, DSP/SPE 2011 - Proceedings. 2011. p. 500-505 5739265.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Xu, Q, Chakrabarti, C & Karam, L 2011, A distributed Canny edge detector and its implementation on FPGA. in 2011 Digital Signal Processing and Signal Processing Education Meeting, DSP/SPE 2011 - Proceedings., 5739265, pp. 500-505, 2011 Digital Signal Processing and Signal Processing Education Meeting, DSP/SPE 2011, Sedona, AZ, United States, 1/4/11. https://doi.org/10.1109/DSP-SPE.2011.5739265
Xu Q, Chakrabarti C, Karam L. A distributed Canny edge detector and its implementation on FPGA. In 2011 Digital Signal Processing and Signal Processing Education Meeting, DSP/SPE 2011 - Proceedings. 2011. p. 500-505. 5739265 https://doi.org/10.1109/DSP-SPE.2011.5739265
Xu, Qian ; Chakrabarti, Chaitali ; Karam, Lina. / A distributed Canny edge detector and its implementation on FPGA. 2011 Digital Signal Processing and Signal Processing Education Meeting, DSP/SPE 2011 - Proceedings. 2011. pp. 500-505
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