A digital PLL based 2                         nd                         -order ?s bandpass time-interleaved ADC

Sanjeev Tannirkulam Chandrasekaran; Arindam Sanyal

doi:10.1109/MWSCAS.2018.8623928

A digital PLL based 2 ^nd -order ?s bandpass time-interleaved ADC

Sanjeev Tannirkulam Chandrasekaran, Arindam Sanyal

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

This paper presents a time-interleaved (TI) VCO-based band-pass ADC with a second-order bandstop noise transfer function. The proposed ADC uses a digital phase-locked loop (PLL) based architecture and employs current starved ring-oscillator as integrator which provides inherent multi-bit quantization. Thus, the proposed band-pass ADC does not need op-amps for integration and consumes low power and area. The proposed ADC is designed in 65nm CMOS and Matlab and Spectre simulations were performed to characterize the ADC. The proposed ADC achieves 61dB SNDR while consuming 0.44mW and has a Walden FoM of 63fJ/conv. step.

Original language	English (US)
Title of host publication	2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	286-289
Number of pages	4
ISBN (Electronic)	9781538673928
DOIs	https://doi.org/10.1109/MWSCAS.2018.8623928
State	Published - Jan 22 2019
Externally published	Yes
Event	61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 - Windsor, Canada Duration: Aug 5 2018 → Aug 8 2018

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	2018-August
ISSN (Print)	1548-3746

Conference

Conference	61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
Country/Territory	Canada
City	Windsor
Period	8/5/18 → 8/8/18

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/MWSCAS.2018.8623928

Cite this

Chandrasekaran, S. T., & Sanyal, A. (2019). A digital PLL based 2 ^nd -order ?s bandpass time-interleaved ADC In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018 (pp. 286-289). Article 8623928 (Midwest Symposium on Circuits and Systems; Vol. 2018-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.2018.8623928

A digital PLL based 2 ^nd -order ?s bandpass time-interleaved ADC . / Chandrasekaran, Sanjeev Tannirkulam; Sanyal, Arindam.
2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 286-289 8623928 (Midwest Symposium on Circuits and Systems; Vol. 2018-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chandrasekaran, ST & Sanyal, A 2019, A digital PLL based 2 ^nd -order ?s bandpass time-interleaved ADC in 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018., 8623928, Midwest Symposium on Circuits and Systems, vol. 2018-August, Institute of Electrical and Electronics Engineers Inc., pp. 286-289, 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, Canada, 8/5/18. https://doi.org/10.1109/MWSCAS.2018.8623928

Chandrasekaran ST, Sanyal A. A digital PLL based 2 ^nd -order ?s bandpass time-interleaved ADC In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 286-289. 8623928. (Midwest Symposium on Circuits and Systems). doi: 10.1109/MWSCAS.2018.8623928

Chandrasekaran, Sanjeev Tannirkulam ; Sanyal, Arindam. / A digital PLL based 2 ^nd -order ?s bandpass time-interleaved ADC 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 286-289 (Midwest Symposium on Circuits and Systems).

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abstract = "This paper presents a time-interleaved (TI) VCO-based band-pass ADC with a second-order bandstop noise transfer function. The proposed ADC uses a digital phase-locked loop (PLL) based architecture and employs current starved ring-oscillator as integrator which provides inherent multi-bit quantization. Thus, the proposed band-pass ADC does not need op-amps for integration and consumes low power and area. The proposed ADC is designed in 65nm CMOS and Matlab and Spectre simulations were performed to characterize the ADC. The proposed ADC achieves 61dB SNDR while consuming 0.44mW and has a Walden FoM of 63fJ/conv. step.",

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note = "Funding Information: This work is supported by Semiconductor Research Corporation (SRC) task # 2712.020 through The University of Texas at Dallas' Texas Analog Center of Excellence (TxACE). Funding Information: V. ACKNOWLEDGMENT This work is supported by Semiconductor Research Corporation (SRC) task # 2712.020 through The University of Texas at Dallas{\textquoteright} Texas Analog Center of Excellence (TxACE). Publisher Copyright: {\textcopyright} 2018 IEEE; 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 ; Conference date: 05-08-2018 Through 08-08-2018",

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