A Design of a Fast and Area Efficient Multi-Input Muller C-element

Tzyh Yung Wuu, Sarma B.K. Vrudhula

Research output: Contribution to journalArticle

34 Scopus citations

Abstract

A multi-input Muller C-element has frequently been used for joining signal transitions or completion time detection in self-timed circuits. This paper presents an n-input Muller C-element design which uses the multi-level login design technique and has a symmetric format for any integer n > 2. In comparison with series-parallel MOS structure implementations and C-element tree implementations, our design has fewer restrictions in terms of n, less path delay, less delay variance from inputs to output, and less area consumption. Experimental validation in this paper is based on an industrial standard cell library.

Original languageEnglish (US)
Pages (from-to)215-219
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume1
Issue number2
DOIs
StatePublished - Jun 1993

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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