### Abstract

Scaling is currently the most popular technique used to improve performance metrics of CMOS circuits. This cannot go on forever because the properties that are responsible for the functioning of MOSFETs no longer hold in nano dimensions. Recent research into nano devices has shown that nano devices can be an alternative to CMOS when scaling of CMOS becomes infeasible in the near future. This is motivating the need for stable and mature design automation techniques for threshold logic since it is the design abstraction used for most nano-devices. Threshold logic (TL) has long been known as an alternative way to compute Boolean function. Much of the earlier work on TL dates back to the 1960s, which focused primarily on exploring the theoretical aspects, with little attention being paid to the synthesis and optimization of large, multi-level TL networks. The lack of efficient implementations of TL gates, when compared to static fully complementary MOS transistor networks and the rapid development of synthesis and optimization tools for Boolean logic design, led to a loss of interest in developing similar infrastructure for designing TL circuits. Recently there has been a resurgence in this field due to the availability of nano-devices and specialized CMOS circuits that are based on threshold logic. However, present methods are unsatisfactory and can be extremely expensive in computation time. Researchers at Arizona State University have developed a new invention that is a new approach for the synthesis of multi-level threshold logic circuits. The key feature of the method is the determination of whether or not a given Boolean function is a threshold function. The traditional approach of doing this is based on determining the satisfiability of a large number of integer linear inequalities. Such a method is only practical for functions with a few inputs. The present invention eliminates the use of linear programming to determine weights and threshold for a threshold function. The theory of the invention is based on a new factorization of a sum-of-product (SOP) of a Boolean function. The new factorization is used to decompose a Boolean function into its constituent threshold functions. The inventors develop a new threshold logic synthesis methodology that uses the decomposition theory. This synthesis methodology produces circuits that are better than the previous state of art (27% better gate count and comparable circuit depth). Potential Applications Post CMOS Devices Resonant Tunneling Diodes (RTDs) Single Electron Transistors (SETs) Quantum Cellular Automata (QCA) Carbon Nano-Tube FETs (CNT-FETs) Benefits and Advantages Provides combinatorial method and a theoretical underpinning for synthesizing TL circuits as opposed to the heuristic of localized merging of Boolean gates Much faster when compared to previous methods, an execution that would take over a minute is accomplished in 2 seconds on average with proposed technology. This synthesis methodology produces circuits that are better than the previous state of art (27% better gate count and comparable circuit depth) Download Original PDF

Original language | English (US) |
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Publication status | Published - Mar 4 2008 |