TY - GEN
T1 - A DC-DC digitally controlled buck regulator utilizing multi-bit Σ-Δ frequency discriminators
AU - Ahmad, Hani
AU - Bakkaloglu, Bertan
PY - 2008
Y1 - 2008
N2 - This paper describes a novel feedback digitization architecture for a digitally controlled PWM DC-DC buck converter. A multi-bit Σ-Δ frequency discriminators (MB-SDFD) is used. This multi-bit parallelization technique is an extension to the first-order Σ-Δ frequency discriminators (SDFD) concept. SDFD concept is based on a non-feedback Σ-Δ modulator that uses FM signal as its input and it outputs stream of bits (ones and zeros) with quantization noise being first-order shaped similar to the traditional Σ-Δ modulators. The output of the multi-bit discriminator is decimated to obtain a higher resolution depending on the output ripple specifications. A block diagram and a behavioral model are presented along with simulation results. Based on 1% allowed output voltage ripple, an 8-bit ADC resolution is achieved using a reference clock frequency of 1MHz. This architecture is flexible and scalable and can fully be implemented in standard digital CMOS.
AB - This paper describes a novel feedback digitization architecture for a digitally controlled PWM DC-DC buck converter. A multi-bit Σ-Δ frequency discriminators (MB-SDFD) is used. This multi-bit parallelization technique is an extension to the first-order Σ-Δ frequency discriminators (SDFD) concept. SDFD concept is based on a non-feedback Σ-Δ modulator that uses FM signal as its input and it outputs stream of bits (ones and zeros) with quantization noise being first-order shaped similar to the traditional Σ-Δ modulators. The output of the multi-bit discriminator is decimated to obtain a higher resolution depending on the output ripple specifications. A block diagram and a behavioral model are presented along with simulation results. Based on 1% allowed output voltage ripple, an 8-bit ADC resolution is achieved using a reference clock frequency of 1MHz. This architecture is flexible and scalable and can fully be implemented in standard digital CMOS.
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U2 - 10.1109/APEC.2008.4522930
DO - 10.1109/APEC.2008.4522930
M3 - Conference contribution
AN - SCOPUS:49249084738
SN - 9781424418749
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 1543
EP - 1548
BT - 2008 23rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC
T2 - 2008 23rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC
Y2 - 24 February 2008 through 28 February 2008
ER -