This paper describes a novel feedback digitization architecture for a digitally controlled PWM DC-DC buck converter. A combination of a VCO followed by an all digital first-order Σ-Δ frequency discriminators (SDFD) is used as a feedback analog-to-digital converter (ADC). The output of the discriminator is decimated to obtain a higher resolution depending on the output ripple specifications. A block diagram and a behavioral model are presented along with simulation results. Based on 1% allowed output voltage ripple, a 8-bit ADC resolution is achieved using a reference clock frequency of 16MHz. Since the SNR of this ADC is a strong function of sampling clock frequency and carrier frequency deviation, it is easy to achieve higher accuracy (resolution) to satisfy wide range of regulation and accuracy requirements. This architecture is flexible and scalable and can fully be implemented in standard digital CMOS.