A DC-DC digitally controlled buck regulator utilizing first-order Σ-Δ frequency discriminators

Hani Ahmad, Bertan Bakkaloglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

This paper describes a novel feedback digitization architecture for a digitally controlled PWM DC-DC buck converter. A combination of a VCO followed by an all digital first-order Σ-Δ frequency discriminators (SDFD) is used as a feedback analog-to-digital converter (ADC). The output of the discriminator is decimated to obtain a higher resolution depending on the output ripple specifications. A block diagram and a behavioral model are presented along with simulation results. Based on 1% allowed output voltage ripple, a 8-bit ADC resolution is achieved using a reference clock frequency of 16MHz. Since the SNR of this ADC is a strong function of sampling clock frequency and carrier frequency deviation, it is easy to achieve higher accuracy (resolution) to satisfy wide range of regulation and accuracy requirements. This architecture is flexible and scalable and can fully be implemented in standard digital CMOS.

Original languageEnglish (US)
Title of host publication2008 23rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC
Pages346-352
Number of pages7
DOIs
StatePublished - Aug 18 2008
Event2008 23rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC - Austin, TX, United States
Duration: Feb 24 2008Feb 28 2008

Publication series

NameConference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

Other

Other2008 23rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC
CountryUnited States
CityAustin, TX
Period2/24/082/28/08

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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