Abstract
A 0.16 mW, 2.3Volt multi-channel digitally controlled oscillator (MDCO) core is designed in a 0.6 micron CMOS process and its prototype design is mapped on an Altera FPGA that can be used for clock recovery applications. This architecture is suitable for digital wireless and cable transceivers that use different bands for transmit and receive modes. As crystal-based-delay cells control its dominant propagation delay, we have obtained a reduced phase-noise in comparison to recently published analog-based DCOs.
Original language | English (US) |
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Title of host publication | Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 319-322 |
Number of pages | 4 |
ISBN (Print) | 0780383206, 9780780383203 |
DOIs | |
State | Published - 2003 |
Externally published | Yes |
Event | 2nd International Conference on Field Programmable Technology, FPT 2003 - Tokyo, Japan Duration: Dec 15 2003 → Dec 17 2003 |
Other
Other | 2nd International Conference on Field Programmable Technology, FPT 2003 |
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Country/Territory | Japan |
City | Tokyo |
Period | 12/15/03 → 12/17/03 |
ASJC Scopus subject areas
- Computer Science Applications
- Software