A component-based simulator for MIPS32 processors

Processor concepts, implementation details, and performance analysis are fundamental in computer architecture education, and MIPS (microprocessor without interlocked pipeline stages) processor designs are used by many universities in teaching the subject. In this paper we present a MIPS32 processor simulator, which enriches students' learning and instructors' teaching experiences. A family of single-cycle, multi-cycle, and pipeline processor models for the MIPS32 architecture are developed according to the parallel Discrete Event System Specification (DEVS) modeling formalism. A collection of elementary sequential and combinational model components along with the processor models are implemented in DEVS-Suite. The simulator supports multi-level model abstractions, register-transfer level animation, performance data collection, and time-based trajectory observation. These features, which are partially supported by a few existing simulators, enable important structural and behavioral details of computer architectures to be described and understood. The MIPS processor models can be reused and systematically extended for modeling and simulating other MIPS processors.