A compiler optimization to reduce soft errors in register files

Jongeun Lee, Aviral Shrivastava

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Abstract

Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing critical path of the processor, but also since it is one of the hottest blocks on the chip, and therefore adding any extra circuitry to it is not desirable. Pure software approaches would be ideal in this case, but previous approaches that are based on program duplication have very significant runtime overheads, and others based on instruction scheduling are only moderately effective due to local scope. We show that the problem of protecting registers inherently requires inter-procedural analysis, and intra-procedural optimization are ineffective. This paper presents a pure compiler approach, based on inter-procedural code analysis to reduce the vulnerability of registers by temporarily writing live variables to protected memory. We formulate the problem as an integer linear programming problem and also present a very efficient heuristic algorithm. Our experiments demonstrate that our proposed technique can reduce the vulnerability of the RF by 33 ̃ 37% on average and up to 66%, with a small 2% increase in runtime. In addition, our overhead reduction optimizations can effectively reduce the code size overhead, by more than 40% on average, to a mere 5 ̃ 6%, as compared to highly optimized binaries.

Original languageEnglish (US)
Title of host publicationLCTES'09 - Proceedings of the 2009 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems
Pages41-49
Number of pages9
DOIs
StatePublished - Nov 30 2009
Event2009 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES'09 - Dublin, Ireland
Duration: Jun 19 2009Jun 20 2009

Publication series

NameProceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

Conference

Conference2009 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES'09
CountryIreland
CityDublin
Period6/19/096/20/09

Keywords

  • Architectural vulnerability factor
  • Compilation
  • Embedded system
  • Link-time optimization
  • Register file
  • Soft error
  • Static analysis

ASJC Scopus subject areas

  • Software

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  • Cite this

    Lee, J., & Shrivastava, A. (2009). A compiler optimization to reduce soft errors in register files. In LCTES'09 - Proceedings of the 2009 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (pp. 41-49). (Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)). https://doi.org/10.1145/1542452.1542459