A compiler optimization to reduce soft errors in register files

Jongeun Lee, Aviral Shrivastava

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing critical path of the processor, but also since it is one of the hottest blocks on the chip, and therefore adding any extra circuitry to it is not desirable. Pure software approaches would be ideal in this case, but previous approaches that are based on program duplication have very significant runtime overheads, and others based on instruction scheduling are only moderately effective due to local scope. We show that the problem of protecting registers inherently requires inter-procedural analysis, and intra-procedural optimization are ineffective. This paper presents a pure compiler approach, based on inter-procedural code analysis to reduce the vulnerability of registers by temporarily writing live variables to protected memory. We formulate the problem as an integer linear programming problem and also present a very efficient heuristic algorithm. Our experiments demonstrate that our proposed technique can reduce the vulnerability of the RF by 33 ̃ 37% on average and up to 66%, with a small 2% increase in runtime. In addition, our overhead reduction optimizations can effectively reduce the code size overhead, by more than 40% on average, to a mere 5 ̃ 6%, as compared to highly optimized binaries.

Original languageEnglish (US)
Title of host publicationProceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
Pages41-49
Number of pages9
DOIs
StatePublished - 2009
Event2009 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES'09 - Dublin, Ireland
Duration: Jun 19 2009Jun 20 2009

Other

Other2009 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES'09
CountryIreland
CityDublin
Period6/19/096/20/09

Fingerprint

Heuristic algorithms
Linear programming
Redundancy
Scheduling
Data storage equipment
Experiments

Keywords

  • Architectural vulnerability factor
  • Compilation
  • Embedded system
  • Link-time optimization
  • Register file
  • Soft error
  • Static analysis

ASJC Scopus subject areas

  • Software

Cite this

Lee, J., & Shrivastava, A. (2009). A compiler optimization to reduce soft errors in register files. In Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES) (pp. 41-49) https://doi.org/10.1145/1542452.1542459

A compiler optimization to reduce soft errors in register files. / Lee, Jongeun; Shrivastava, Aviral.

Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). 2009. p. 41-49.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lee, J & Shrivastava, A 2009, A compiler optimization to reduce soft errors in register files. in Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). pp. 41-49, 2009 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES'09, Dublin, Ireland, 6/19/09. https://doi.org/10.1145/1542452.1542459
Lee J, Shrivastava A. A compiler optimization to reduce soft errors in register files. In Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). 2009. p. 41-49 https://doi.org/10.1145/1542452.1542459
Lee, Jongeun ; Shrivastava, Aviral. / A compiler optimization to reduce soft errors in register files. Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). 2009. pp. 41-49
@inproceedings{d1c04ea2b0c84064b69c78ff4293c4f9,
title = "A compiler optimization to reduce soft errors in register files",
abstract = "Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing critical path of the processor, but also since it is one of the hottest blocks on the chip, and therefore adding any extra circuitry to it is not desirable. Pure software approaches would be ideal in this case, but previous approaches that are based on program duplication have very significant runtime overheads, and others based on instruction scheduling are only moderately effective due to local scope. We show that the problem of protecting registers inherently requires inter-procedural analysis, and intra-procedural optimization are ineffective. This paper presents a pure compiler approach, based on inter-procedural code analysis to reduce the vulnerability of registers by temporarily writing live variables to protected memory. We formulate the problem as an integer linear programming problem and also present a very efficient heuristic algorithm. Our experiments demonstrate that our proposed technique can reduce the vulnerability of the RF by 33 ̃ 37{\%} on average and up to 66{\%}, with a small 2{\%} increase in runtime. In addition, our overhead reduction optimizations can effectively reduce the code size overhead, by more than 40{\%} on average, to a mere 5 ̃ 6{\%}, as compared to highly optimized binaries.",
keywords = "Architectural vulnerability factor, Compilation, Embedded system, Link-time optimization, Register file, Soft error, Static analysis",
author = "Jongeun Lee and Aviral Shrivastava",
year = "2009",
doi = "10.1145/1542452.1542459",
language = "English (US)",
isbn = "9781605583563",
pages = "41--49",
booktitle = "Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)",

}

TY - GEN

T1 - A compiler optimization to reduce soft errors in register files

AU - Lee, Jongeun

AU - Shrivastava, Aviral

PY - 2009

Y1 - 2009

N2 - Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing critical path of the processor, but also since it is one of the hottest blocks on the chip, and therefore adding any extra circuitry to it is not desirable. Pure software approaches would be ideal in this case, but previous approaches that are based on program duplication have very significant runtime overheads, and others based on instruction scheduling are only moderately effective due to local scope. We show that the problem of protecting registers inherently requires inter-procedural analysis, and intra-procedural optimization are ineffective. This paper presents a pure compiler approach, based on inter-procedural code analysis to reduce the vulnerability of registers by temporarily writing live variables to protected memory. We formulate the problem as an integer linear programming problem and also present a very efficient heuristic algorithm. Our experiments demonstrate that our proposed technique can reduce the vulnerability of the RF by 33 ̃ 37% on average and up to 66%, with a small 2% increase in runtime. In addition, our overhead reduction optimizations can effectively reduce the code size overhead, by more than 40% on average, to a mere 5 ̃ 6%, as compared to highly optimized binaries.

AB - Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing critical path of the processor, but also since it is one of the hottest blocks on the chip, and therefore adding any extra circuitry to it is not desirable. Pure software approaches would be ideal in this case, but previous approaches that are based on program duplication have very significant runtime overheads, and others based on instruction scheduling are only moderately effective due to local scope. We show that the problem of protecting registers inherently requires inter-procedural analysis, and intra-procedural optimization are ineffective. This paper presents a pure compiler approach, based on inter-procedural code analysis to reduce the vulnerability of registers by temporarily writing live variables to protected memory. We formulate the problem as an integer linear programming problem and also present a very efficient heuristic algorithm. Our experiments demonstrate that our proposed technique can reduce the vulnerability of the RF by 33 ̃ 37% on average and up to 66%, with a small 2% increase in runtime. In addition, our overhead reduction optimizations can effectively reduce the code size overhead, by more than 40% on average, to a mere 5 ̃ 6%, as compared to highly optimized binaries.

KW - Architectural vulnerability factor

KW - Compilation

KW - Embedded system

KW - Link-time optimization

KW - Register file

KW - Soft error

KW - Static analysis

UR - http://www.scopus.com/inward/record.url?scp=70450285520&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70450285520&partnerID=8YFLogxK

U2 - 10.1145/1542452.1542459

DO - 10.1145/1542452.1542459

M3 - Conference contribution

AN - SCOPUS:70450285520

SN - 9781605583563

SP - 41

EP - 49

BT - Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

ER -