A comparator-based rail clamp for handling electrostatic discharge (ESD) events is presented. The new circuit technique allows the use of a time constant that can be much smaller than a traditional RC and inverter-based clamp. The new clamp is more area-efficient and dissipates ESD events with little residual energy. The design is able to support applications with power-ON time slower than 4 μs, is immune to latch-ON, and recovers very quickly if falsely triggered. Experimental results and performance comparisons with the traditional circuit are presented.
|Original language||English (US)|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Accepted/In press - Jul 20 2015|
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture