A Compact Model for Metal-Oxide Resistive Random Access Memory With Experiment Verification

Zizhen Jiang, Yi Wu, Shimeng Yu, Lin Yang, Kay Song, Zia Karim, H. S Philip Wong

Research output: Contribution to journalArticle

47 Citations (Scopus)

Abstract

A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array.

Original languageEnglish (US)
JournalIEEE Transactions on Electron Devices
DOIs
StateAccepted/In press - Apr 7 2016

Fingerprint

Oxides
Metals
Data storage equipment
Associative storage
Experiments
Macros
Computer hardware description languages
Multilayers
Energy utilization
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

A Compact Model for Metal-Oxide Resistive Random Access Memory With Experiment Verification. / Jiang, Zizhen; Wu, Yi; Yu, Shimeng; Yang, Lin; Song, Kay; Karim, Zia; Wong, H. S Philip.

In: IEEE Transactions on Electron Devices, 07.04.2016.

Research output: Contribution to journalArticle

Jiang, Zizhen ; Wu, Yi ; Yu, Shimeng ; Yang, Lin ; Song, Kay ; Karim, Zia ; Wong, H. S Philip. / A Compact Model for Metal-Oxide Resistive Random Access Memory With Experiment Verification. In: IEEE Transactions on Electron Devices. 2016.
@article{6aaf9eeb24a1496d97e2dcdbdef111ea,
title = "A Compact Model for Metal-Oxide Resistive Random Access Memory With Experiment Verification",
abstract = "A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array.",
author = "Zizhen Jiang and Yi Wu and Shimeng Yu and Lin Yang and Kay Song and Zia Karim and Wong, {H. S Philip}",
year = "2016",
month = "4",
day = "7",
doi = "10.1109/TED.2016.2545412",
language = "English (US)",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - A Compact Model for Metal-Oxide Resistive Random Access Memory With Experiment Verification

AU - Jiang, Zizhen

AU - Wu, Yi

AU - Yu, Shimeng

AU - Yang, Lin

AU - Song, Kay

AU - Karim, Zia

AU - Wong, H. S Philip

PY - 2016/4/7

Y1 - 2016/4/7

N2 - A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array.

AB - A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array.

UR - http://www.scopus.com/inward/record.url?scp=84979492576&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84979492576&partnerID=8YFLogxK

U2 - 10.1109/TED.2016.2545412

DO - 10.1109/TED.2016.2545412

M3 - Article

AN - SCOPUS:84979492576

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

ER -