A Compact model for metal-oxide resistive random access memory with experiment verification

Zizhen Jiang, Yi Wu, Shimeng Yu, Lin Yang, Kay Song, Zia Karim, H. S Philip Wong

Research output: Contribution to journalArticlepeer-review

71 Scopus citations

Abstract

A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array.

Original languageEnglish (US)
Article number7448912
Pages (from-to)1884-1892
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume63
Issue number5
DOIs
StatePublished - May 2016

Keywords

  • Compact model
  • OXRAM
  • ReRAM
  • Verilog-A.
  • experimental verification
  • resistive random access memory (RRAM)
  • variations

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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