A combinatorial approach to X-tolerant compaction circuits

Yuichiro Fujiwara, Charles Colbourn

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

Test response compaction for integrated circuits (ICs) with scan-based design-for-testability (DFT) support in the presence of unknown logic values (Xs) is investigated from a combinatorial viewpoint. The theoretical foundations of X-codes, employed in an X-tolerant compaction technique called X-compact, are examined. Through the formulation of a combinatorial model of X-compact, novel design techniques are developed for X-codes to detect a specified maximum number of errors in the presence of a specified maximum number of unknown logic values, while requiring only small fan-out. The special class of X-codes that results leads to an avoidance problem for configurations in combinatorial designs. General design methods and nonconstructive existence theorems to estimate the compaction ratio of an optimal X-compactor are also derived.

Original languageEnglish (US)
Article number5485008
Pages (from-to)3196-3206
Number of pages11
JournalIEEE Transactions on Information Theory
Volume56
Issue number7
DOIs
StatePublished - Jul 2010

Fingerprint

Compaction
Networks (circuits)
fan
Design for testability
Values
Fans
Integrated circuits

Keywords

  • Built-in self-test (BIST)
  • Circuit testing
  • Compaction
  • Configuration
  • Steiner system
  • Superimposed code
  • Test compression
  • X-code
  • X-compact

ASJC Scopus subject areas

  • Information Systems
  • Computer Science Applications
  • Library and Information Sciences

Cite this

A combinatorial approach to X-tolerant compaction circuits. / Fujiwara, Yuichiro; Colbourn, Charles.

In: IEEE Transactions on Information Theory, Vol. 56, No. 7, 5485008, 07.2010, p. 3196-3206.

Research output: Contribution to journalArticle

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