Abstract
A new method for reducing power and area of standard cell ASICs is described. The method is based on deliberately introducing clock skew without the use of extra buffers in the clock network. This is done by having some flipflops, called sources, generate clock signals for other flipflops, called targets. The method involves two key features: (1) the design of new differential flipflop, referred to as KVFF, that is functionally identical to a master-slave edge-Triggered D flipflop, but in addition, produces an completion signal that is a skewed version of its input clock, which is used to clock other flipflops; and (2) an efficient algorithm that identifies the sources and targets involved in the new clocking scheme, with the objective of reducing area and power. These are reduced because deliberate skew introduces extra slack on the logic cones that feed the target flipflops, which is exploited by synthesis tools to reduce area and power. In addition, the overhead of conventional methods of introducing skew, e.g. buffers, is eliminated. Using commercial tools, significant improvements in power and area are shown on placed and routed netlists of several circuits.
Original language | English (US) |
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Title of host publication | Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Volume | Part 128280 |
ISBN (Electronic) | 9781450349277 |
DOIs | |
State | Published - Jun 18 2017 |
Event | 54th Annual Design Automation Conference, DAC 2017 - Austin, United States Duration: Jun 18 2017 → Jun 22 2017 |
Other
Other | 54th Annual Design Automation Conference, DAC 2017 |
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Country/Territory | United States |
City | Austin |
Period | 6/18/17 → 6/22/17 |
ASJC Scopus subject areas
- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modeling and Simulation