TY - GEN
T1 - A built-in self-test technique for load inductance and lossless current sensing of DC-DC converters
AU - Liu, Tao
AU - Fu, Chao
AU - Ozev, Sule
AU - Bakkaloglu, Bertan
PY - 2014/1/1
Y1 - 2014/1/1
N2 - One of the major problems associated with integrated DC-DC converters used in state of the art Power Management ICs (PMICs) is dynamic performance and stability degradation due to off-chip component and output current variations. A high accuracy built-in self-test (BIST) architecture measuring load inductance and DC resistance (DCR) of DC-DC converters is presented. The DCR measurement of the inductor also enables continuous, lossless average load current sensing of the DC-DC converter across the inductor. Both the BIST circuit and the primary signal chain utilize low analog complexity frequency-domain ΔΣADC. The ΔΣADC decimation filter nulls also provide current ripple cancellation and average current extraction. The BIST module can measure filter inductance values ranging from 3.6μH to 22.3μH range with average 2.0% error and inductor DCR 13mΩ to 68mΩ range with average 2.1% error. The average current sensing enabled by the BIST technique achieves current measurement accuracy with average 2.3% error for 0.1A-1A range load current. BIST and current sensing modules occupy less than 6% of total chip area. The BIST circuitry is fabricated and tested with a 12V input, 1V-11.5V output range, for a 3W output power digital DC-DC converter.
AB - One of the major problems associated with integrated DC-DC converters used in state of the art Power Management ICs (PMICs) is dynamic performance and stability degradation due to off-chip component and output current variations. A high accuracy built-in self-test (BIST) architecture measuring load inductance and DC resistance (DCR) of DC-DC converters is presented. The DCR measurement of the inductor also enables continuous, lossless average load current sensing of the DC-DC converter across the inductor. Both the BIST circuit and the primary signal chain utilize low analog complexity frequency-domain ΔΣADC. The ΔΣADC decimation filter nulls also provide current ripple cancellation and average current extraction. The BIST module can measure filter inductance values ranging from 3.6μH to 22.3μH range with average 2.0% error and inductor DCR 13mΩ to 68mΩ range with average 2.1% error. The average current sensing enabled by the BIST technique achieves current measurement accuracy with average 2.3% error for 0.1A-1A range load current. BIST and current sensing modules occupy less than 6% of total chip area. The BIST circuitry is fabricated and tested with a 12V input, 1V-11.5V output range, for a 3W output power digital DC-DC converter.
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U2 - 10.1109/VTS.2014.6818750
DO - 10.1109/VTS.2014.6818750
M3 - Conference contribution
AN - SCOPUS:84901918985
SN - 9781479926114
T3 - Proceedings of the IEEE VLSI Test Symposium
BT - Proceedings - 2014 IEEE 32nd VLSI Test Symposium, VTS 2014
PB - IEEE Computer Society
T2 - 2014 IEEE 32nd VLSI Test Symposium, VTS 2014
Y2 - 13 April 2014 through 17 April 2014
ER -