A 90nm CMOS 5GHz ring oscillator PLL with delay-discriminator based active phase noise cancellation

Seungkee Min; Tino Copani; Sayfe Kiaei; Bertan Bakkaloglu

doi:10.1109/RFIC.2012.6242257

A 90nm CMOS 5GHz ring oscillator PLL with delay-discriminator based active phase noise cancellation

Seungkee Min, Tino Copani, Sayfe Kiaei, Bertan Bakkaloglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Scopus citations

Abstract

Ring-oscillators provide a low-cost digital VCO solution in fully integrated PLLs, but due to their supply noise sensitivity and high noise floor, their applications have been limited. A fully integrated feed-forward, delay-discriminator based adaptive noise-cancellation architecture that improves phase noise characteristic of ring-oscillators outside the PLL bandwidth is presented. Proposed technique can improve the phase noise in an arbitrary offset frequency and bandwidth, and it is insensitive to process and temperature variations. The proposed cancellation loop suppresses the phase noise at 1 MHz offset by 12.5dB and reference spur by 13dB, with 3.7mA power consumption. The measured phase noise at 1 MHz offset is -105 dBc/Hz. The proposed PLL is fabricated in 90 nm CMOS with current consumption of 24.7 mA with the cancellation technique enabled from a voltage supply of 1.2 V.

Original language	English (US)
Title of host publication	2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers
Pages	173-176
Number of pages	4
DOIs	https://doi.org/10.1109/RFIC.2012.6242257
State	Published - Sep 28 2012
Event	2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Montreal, QC, Canada Duration: Jun 17 2012 → Jun 19 2012

Publication series

Name	Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)	1529-2517

Other

Other	2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012
Country/Territory	Canada
City	Montreal, QC
Period	6/17/12 → 6/19/12

Keywords

Delay-discriminator
frequency synthesizer
phase-locked loop (PLL)
ring oscillator VCO

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/RFIC.2012.6242257

Cite this

Min, S., Copani, T., Kiaei, S., & Bakkaloglu, B. (2012). A 90nm CMOS 5GHz ring oscillator PLL with delay-discriminator based active phase noise cancellation. In 2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers (pp. 173-176). [6242257] (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). https://doi.org/10.1109/RFIC.2012.6242257

A 90nm CMOS 5GHz ring oscillator PLL with delay-discriminator based active phase noise cancellation. / Min, Seungkee; Copani, Tino; Kiaei, Sayfe et al.
2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers. 2012. p. 173-176 6242257 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Min, S, Copani, T, Kiaei, S & Bakkaloglu, B 2012, A 90nm CMOS 5GHz ring oscillator PLL with delay-discriminator based active phase noise cancellation. in 2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers., 6242257, Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, pp. 173-176, 2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012, Montreal, QC, Canada, 6/17/12. https://doi.org/10.1109/RFIC.2012.6242257

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abstract = "Ring-oscillators provide a low-cost digital VCO solution in fully integrated PLLs, but due to their supply noise sensitivity and high noise floor, their applications have been limited. A fully integrated feed-forward, delay-discriminator based adaptive noise-cancellation architecture that improves phase noise characteristic of ring-oscillators outside the PLL bandwidth is presented. Proposed technique can improve the phase noise in an arbitrary offset frequency and bandwidth, and it is insensitive to process and temperature variations. The proposed cancellation loop suppresses the phase noise at 1 MHz offset by 12.5dB and reference spur by 13dB, with 3.7mA power consumption. The measured phase noise at 1 MHz offset is -105 dBc/Hz. The proposed PLL is fabricated in 90 nm CMOS with current consumption of 24.7 mA with the cancellation technique enabled from a voltage supply of 1.2 V.",

keywords = "Delay-discriminator, frequency synthesizer, phase-locked loop (PLL), ring oscillator VCO",

author = "Seungkee Min and Tino Copani and Sayfe Kiaei and Bertan Bakkaloglu",

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PY - 2012/9/28

Y1 - 2012/9/28

N2 - Ring-oscillators provide a low-cost digital VCO solution in fully integrated PLLs, but due to their supply noise sensitivity and high noise floor, their applications have been limited. A fully integrated feed-forward, delay-discriminator based adaptive noise-cancellation architecture that improves phase noise characteristic of ring-oscillators outside the PLL bandwidth is presented. Proposed technique can improve the phase noise in an arbitrary offset frequency and bandwidth, and it is insensitive to process and temperature variations. The proposed cancellation loop suppresses the phase noise at 1 MHz offset by 12.5dB and reference spur by 13dB, with 3.7mA power consumption. The measured phase noise at 1 MHz offset is -105 dBc/Hz. The proposed PLL is fabricated in 90 nm CMOS with current consumption of 24.7 mA with the cancellation technique enabled from a voltage supply of 1.2 V.

AB - Ring-oscillators provide a low-cost digital VCO solution in fully integrated PLLs, but due to their supply noise sensitivity and high noise floor, their applications have been limited. A fully integrated feed-forward, delay-discriminator based adaptive noise-cancellation architecture that improves phase noise characteristic of ring-oscillators outside the PLL bandwidth is presented. Proposed technique can improve the phase noise in an arbitrary offset frequency and bandwidth, and it is insensitive to process and temperature variations. The proposed cancellation loop suppresses the phase noise at 1 MHz offset by 12.5dB and reference spur by 13dB, with 3.7mA power consumption. The measured phase noise at 1 MHz offset is -105 dBc/Hz. The proposed PLL is fabricated in 90 nm CMOS with current consumption of 24.7 mA with the cancellation technique enabled from a voltage supply of 1.2 V.

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A 90nm CMOS 5GHz ring oscillator PLL with delay-discriminator based active phase noise cancellation

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