A 90nm CMOS 5GHz ring oscillator PLL with delay-discriminator based active phase noise cancellation

Seungkee Min, Tino Copani, Sayfe Kiaei, Bertan Bakkaloglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

Ring-oscillators provide a low-cost digital VCO solution in fully integrated PLLs, but due to their supply noise sensitivity and high noise floor, their applications have been limited. A fully integrated feed-forward, delay-discriminator based adaptive noise-cancellation architecture that improves phase noise characteristic of ring-oscillators outside the PLL bandwidth is presented. Proposed technique can improve the phase noise in an arbitrary offset frequency and bandwidth, and it is insensitive to process and temperature variations. The proposed cancellation loop suppresses the phase noise at 1 MHz offset by 12.5dB and reference spur by 13dB, with 3.7mA power consumption. The measured phase noise at 1 MHz offset is -105 dBc/Hz. The proposed PLL is fabricated in 90 nm CMOS with current consumption of 24.7 mA with the cancellation technique enabled from a voltage supply of 1.2 V.

Original languageEnglish (US)
Title of host publication2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers
Pages173-176
Number of pages4
DOIs
StatePublished - 2012
Event2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Montreal, QC, Canada
Duration: Jun 17 2012Jun 19 2012

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)1529-2517

Other

Other2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012
Country/TerritoryCanada
CityMontreal, QC
Period6/17/126/19/12

Keywords

  • Delay-discriminator
  • frequency synthesizer
  • phase-locked loop (PLL)
  • ring oscillator VCO

ASJC Scopus subject areas

  • General Engineering

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