A 700uA, 405MHz fractional-N all digital frequency-locked loop for MICS band applications

S. Shashidharan, W. Khalil, S. Chakraborty, Sayfe Kiaei, T. Copani, Bertan Bakkaloglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Abstract

An all-digital frequency-locked loop (ADFLL) based frequency synthesizer with a built-in FSK modulator for medical implants communication systems (MICS) band applications is presented. The ADFLL uses a high resolution single-bit digital ΣΔ frequency discriminator in the feedback path and a ΣΔ phase accumulator in the reference path, achieving fractional resolution. The ADFLL uses a digital IIR-based loop filter followed by a digital-intensive ΣΔ current-steering DAC and a first-order-hold filter. The ADFLL achieves 9.5Hz frequency resolution, spanning the ISM 400MHz-410MHz band. The worst-case near-integer spur of -55dBc and a phase noise of -83dBc/Hz at 300kHz offset is measured. The ADFLL is fabricated on a 0.18um CMOS process, occupying 0.14mm2 die area, with a quiescent current consumption of 700uA.

Original languageEnglish (US)
Title of host publicationProceedings of the 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010
Pages409-412
Number of pages4
DOIs
StatePublished - Jul 16 2010
Event2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010 - Anaheim, CA, United States
Duration: May 23 2010May 25 2010

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)1529-2517

Other

Other2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010
CountryUnited States
CityAnaheim, CA
Period5/23/105/25/10

Keywords

  • Digital PLLs
  • Type-I PLLs
  • ΣΔ DACs

ASJC Scopus subject areas

  • Engineering(all)

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