A 700-μ A 405-MHz all-digital fractional-N frequency-locked loop for ISM band applications

Waleed Khalil, Sridhar Shashidharan, Tino Copani, Sudipto Chakraborty, Sayfe Kiaei, Bertan Bakkaloglu

Research output: Contribution to journalArticle

29 Scopus citations

Abstract

Several wireless biomedical transceivers, including medical implants communication systems (MICSs), require ultra-low-power low-complexity frequency synthesizers. This paper presents an all-digital frequency-locked loop (ADFLL)-based frequency synthesizer with a built-in frequency-shift keying modulator for MICS and industrialscientificmedical band applications. Unlike all-digital phase-locked loops that rely on a power-hungry time to digital converter, the proposed ADFLL employs a high-resolution single-bit Σ Δ frequency discriminator in the feedback path and a noise-cancelling Σ Δ phase-accumulator-based frequency controller in the reference path, achieving fractional resolution with low power consumption. The loop compensation is implemented digitally using an infinite impulse response filter followed by a digital-intensive current-steering DAC driving a ring-oscillator-based voltage-controlled oscillator. The ADFLL achieves 9.5-Hz frequency resolution, spanning the ISM 400410-MHz band. A worst case near-integer spur of -62 dBc and a phase noise of -83 dBc/Hz at 300-kHz offset are measured. The ADFLL is fabricated on a 0.18-μm CMOS process, occupying a 0.14-mm2 die area, with a quiescent current consumption of 700 μ A.

Original languageEnglish (US)
Article number5737781
Pages (from-to)1319-1326
Number of pages8
JournalIEEE Transactions on Microwave Theory and Techniques
Volume59
Issue number5
DOIs
Publication statusPublished - May 2011

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Keywords

  • Σ Δ phase-locked loops (PLLs)
  • All-digital frequency-locked loops (ADFLLs)
  • frequency-locked loops (FLLs)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Radiation

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