TY - GEN
T1 - A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS
AU - Sanyal, Arindam
AU - Sun, Nan
N1 - Funding Information:
This work was supported in part by NSF grants 1254459, 1509767 and 1527320.
Publisher Copyright:
© 2016 IEEE.
PY - 2016/10/18
Y1 - 2016/10/18
N2 - A highly digital, two-stage capacitance-to-digital converter (CDC) is presented in this work. The CDC works by sampling a reference voltage on the sensing capacitor and then quantizing the charge stored in it by a 9-bit SAR ADC. The residue is fed to a ring VCO and quantized in time domain. The outputs from the two stages are combined to produce a quantized output with first-order noise shaping. A digital background calibration technique is used to track the VCO's gain across PVT. A prototype CDC in 40nm CMOS process achieves 64.2 dB SNR and an FoM of 55fJ/conversion-step while operating from a 1V supply and using a sampling frequency of 3MHz.
AB - A highly digital, two-stage capacitance-to-digital converter (CDC) is presented in this work. The CDC works by sampling a reference voltage on the sensing capacitor and then quantizing the charge stored in it by a 9-bit SAR ADC. The residue is fed to a ring VCO and quantized in time domain. The outputs from the two stages are combined to produce a quantized output with first-order noise shaping. A digital background calibration technique is used to track the VCO's gain across PVT. A prototype CDC in 40nm CMOS process achieves 64.2 dB SNR and an FoM of 55fJ/conversion-step while operating from a 1V supply and using a sampling frequency of 3MHz.
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U2 - 10.1109/ESSCIRC.2016.7598322
DO - 10.1109/ESSCIRC.2016.7598322
M3 - Conference contribution
AN - SCOPUS:84994475069
T3 - European Solid-State Circuits Conference
SP - 385
EP - 388
BT - ESSCIRC 2016
PB - IEEE Computer Society
T2 - 42nd European Solid-State Circuits Conference, ESSCIRC 2016
Y2 - 12 September 2016 through 15 September 2016
ER -