A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

A highly digital, two-stage capacitance-to-digital converter (CDC) is presented in this work. The CDC works by sampling a reference voltage on the sensing capacitor and then quantizing the charge stored in it by a 9-bit SAR ADC. The residue is fed to a ring VCO and quantized in time domain. The outputs from the two stages are combined to produce a quantized output with first-order noise shaping. A digital background calibration technique is used to track the VCO's gain across PVT. A prototype CDC in 40nm CMOS process achieves 64.2 dB SNR and an FoM of 55fJ/conversion-step while operating from a 1V supply and using a sampling frequency of 3MHz.

Original languageEnglish (US)
Title of host publicationESSCIRC 2016
Subtitle of host publication42nd European Solid-State Circuits Conference
PublisherIEEE Computer Society
Pages385-388
Number of pages4
ISBN (Electronic)9781509029723
DOIs
StatePublished - Oct 18 2016
Externally publishedYes
Event42nd European Solid-State Circuits Conference, ESSCIRC 2016 - Lausanne, Switzerland
Duration: Sep 12 2016Sep 15 2016

Publication series

NameEuropean Solid-State Circuits Conference
Volume2016-October
ISSN (Print)1930-8833

Conference

Conference42nd European Solid-State Circuits Conference, ESSCIRC 2016
Country/TerritorySwitzerland
CityLausanne
Period9/12/169/15/16

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS'. Together they form a unique fingerprint.

Cite this