A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS

Arindam Sanyal; Nan Sun

doi:10.1109/ESSCIRC.2016.7598322

A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS

Arindam Sanyal, Nan Sun

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Scopus citations

Abstract

A highly digital, two-stage capacitance-to-digital converter (CDC) is presented in this work. The CDC works by sampling a reference voltage on the sensing capacitor and then quantizing the charge stored in it by a 9-bit SAR ADC. The residue is fed to a ring VCO and quantized in time domain. The outputs from the two stages are combined to produce a quantized output with first-order noise shaping. A digital background calibration technique is used to track the VCO's gain across PVT. A prototype CDC in 40nm CMOS process achieves 64.2 dB SNR and an FoM of 55fJ/conversion-step while operating from a 1V supply and using a sampling frequency of 3MHz.

Original language	English (US)
Title of host publication	ESSCIRC 2016
Subtitle of host publication	42nd European Solid-State Circuits Conference
Publisher	IEEE Computer Society
Pages	385-388
Number of pages	4
ISBN (Electronic)	9781509029723
DOIs	https://doi.org/10.1109/ESSCIRC.2016.7598322
State	Published - Oct 18 2016
Externally published	Yes
Event	42nd European Solid-State Circuits Conference, ESSCIRC 2016 - Lausanne, Switzerland Duration: Sep 12 2016 → Sep 15 2016

Publication series

Name	European Solid-State Circuits Conference
Volume	2016-October
ISSN (Print)	1930-8833

Conference

Conference	42nd European Solid-State Circuits Conference, ESSCIRC 2016
Country/Territory	Switzerland
City	Lausanne
Period	9/12/16 → 9/15/16

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ESSCIRC.2016.7598322

Cite this

A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS. / Sanyal, Arindam; Sun, Nan.
ESSCIRC 2016: 42nd European Solid-State Circuits Conference. IEEE Computer Society, 2016. p. 385-388 7598322 (European Solid-State Circuits Conference; Vol. 2016-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sanyal, A & Sun, N 2016, A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS. in ESSCIRC 2016: 42nd European Solid-State Circuits Conference., 7598322, European Solid-State Circuits Conference, vol. 2016-October, IEEE Computer Society, pp. 385-388, 42nd European Solid-State Circuits Conference, ESSCIRC 2016, Lausanne, Switzerland, 9/12/16. https://doi.org/10.1109/ESSCIRC.2016.7598322

@inproceedings{9466723616ed4951a77c34db1164ed14,

title = "A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS",

abstract = "A highly digital, two-stage capacitance-to-digital converter (CDC) is presented in this work. The CDC works by sampling a reference voltage on the sensing capacitor and then quantizing the charge stored in it by a 9-bit SAR ADC. The residue is fed to a ring VCO and quantized in time domain. The outputs from the two stages are combined to produce a quantized output with first-order noise shaping. A digital background calibration technique is used to track the VCO's gain across PVT. A prototype CDC in 40nm CMOS process achieves 64.2 dB SNR and an FoM of 55fJ/conversion-step while operating from a 1V supply and using a sampling frequency of 3MHz.",

author = "Arindam Sanyal and Nan Sun",

note = "Funding Information: This work was supported in part by NSF grants 1254459, 1509767 and 1527320. Publisher Copyright: {\textcopyright} 2016 IEEE.; 42nd European Solid-State Circuits Conference, ESSCIRC 2016 ; Conference date: 12-09-2016 Through 15-09-2016",

year = "2016",

month = oct,

day = "18",

doi = "10.1109/ESSCIRC.2016.7598322",

language = "English (US)",

series = "European Solid-State Circuits Conference",

publisher = "IEEE Computer Society",

pages = "385--388",

booktitle = "ESSCIRC 2016",

}

TY - GEN

T1 - A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS

AU - Sanyal, Arindam

AU - Sun, Nan

PY - 2016/10/18

Y1 - 2016/10/18

N2 - A highly digital, two-stage capacitance-to-digital converter (CDC) is presented in this work. The CDC works by sampling a reference voltage on the sensing capacitor and then quantizing the charge stored in it by a 9-bit SAR ADC. The residue is fed to a ring VCO and quantized in time domain. The outputs from the two stages are combined to produce a quantized output with first-order noise shaping. A digital background calibration technique is used to track the VCO's gain across PVT. A prototype CDC in 40nm CMOS process achieves 64.2 dB SNR and an FoM of 55fJ/conversion-step while operating from a 1V supply and using a sampling frequency of 3MHz.

AB - A highly digital, two-stage capacitance-to-digital converter (CDC) is presented in this work. The CDC works by sampling a reference voltage on the sensing capacitor and then quantizing the charge stored in it by a 9-bit SAR ADC. The residue is fed to a ring VCO and quantized in time domain. The outputs from the two stages are combined to produce a quantized output with first-order noise shaping. A digital background calibration technique is used to track the VCO's gain across PVT. A prototype CDC in 40nm CMOS process achieves 64.2 dB SNR and an FoM of 55fJ/conversion-step while operating from a 1V supply and using a sampling frequency of 3MHz.

UR - http://www.scopus.com/inward/record.url?scp=84994475069&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84994475069&partnerID=8YFLogxK

U2 - 10.1109/ESSCIRC.2016.7598322

DO - 10.1109/ESSCIRC.2016.7598322

M3 - Conference contribution

AN - SCOPUS:84994475069

T3 - European Solid-State Circuits Conference

SP - 385

EP - 388

BT - ESSCIRC 2016

PB - IEEE Computer Society

T2 - 42nd European Solid-State Circuits Conference, ESSCIRC 2016

Y2 - 12 September 2016 through 15 September 2016

ER -

A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this