A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, José A. Tierno, Leland Chang, Dharmendra S. Modha, Daniel J. Friedman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

180 Citations (Scopus)

Abstract

Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of analog neuron circuits; (b) the enormous area overhead of learning circuits, which grows with the number of synapses; and (c) the need to implement all inter-neuron communication via off-chip address-events. In this work, a new architecture is proposed to overcome these challenges by combining innovations in computation, memory, and communication, respectively, to leverage (a) robust digital neuron circuits; (b) novel transposable SRAM arrays that share learning circuits, which grow only with the number of neurons; and (c) crossbar fan-out for efficient on-chip inter-neuron communication. Through tight integration of memory (synapses) and computation (neurons), a highly configurable chip comprising 256 neurons and 64K binary synapses with on-chip learning based on spike-timing dependent plasticity is demonstrated in 45nm SOI-CMOS. Near-threshold, event-driven operation at 0.53V is demonstrated to maximize power efficiency for real-time pattern classification, recognition, and associative memory tasks. Future scalable systems built from the foundation provided by this work will open up possibilities for ubiquitous ultra-dense, ultra-low power brain-like cognitive computers.

Original languageEnglish (US)
Title of host publicationProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - 2011
Externally publishedYes
Event33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011 - San Jose, CA, United States
Duration: Sep 19 2011Sep 21 2011

Other

Other33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011
CountryUnited States
CitySan Jose, CA
Period9/19/119/21/11

Fingerprint

Neurons
Networks (circuits)
Data storage equipment
Communication
Static random access storage
Learning algorithms
Fans
Pattern recognition
Plasticity
Scalability
Brain
Innovation
Silicon

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Seo, J., Brezzo, B., Liu, Y., Parker, B. D., Esser, S. K., Montoye, R. K., ... Friedman, D. J. (2011). A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. In Proceedings of the Custom Integrated Circuits Conference [6055293] https://doi.org/10.1109/CICC.2011.6055293

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. / Seo, Jae-sun; Brezzo, Bernard; Liu, Yong; Parker, Benjamin D.; Esser, Steven K.; Montoye, Robert K.; Rajendran, Bipin; Tierno, José A.; Chang, Leland; Modha, Dharmendra S.; Friedman, Daniel J.

Proceedings of the Custom Integrated Circuits Conference. 2011. 6055293.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Seo, J, Brezzo, B, Liu, Y, Parker, BD, Esser, SK, Montoye, RK, Rajendran, B, Tierno, JA, Chang, L, Modha, DS & Friedman, DJ 2011, A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. in Proceedings of the Custom Integrated Circuits Conference., 6055293, 33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011, San Jose, CA, United States, 9/19/11. https://doi.org/10.1109/CICC.2011.6055293
Seo J, Brezzo B, Liu Y, Parker BD, Esser SK, Montoye RK et al. A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. In Proceedings of the Custom Integrated Circuits Conference. 2011. 6055293 https://doi.org/10.1109/CICC.2011.6055293
Seo, Jae-sun ; Brezzo, Bernard ; Liu, Yong ; Parker, Benjamin D. ; Esser, Steven K. ; Montoye, Robert K. ; Rajendran, Bipin ; Tierno, José A. ; Chang, Leland ; Modha, Dharmendra S. ; Friedman, Daniel J. / A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. Proceedings of the Custom Integrated Circuits Conference. 2011.
@inproceedings{ed0383447cf7485598be6fcebe3f4e07,
title = "A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons",
abstract = "Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of analog neuron circuits; (b) the enormous area overhead of learning circuits, which grows with the number of synapses; and (c) the need to implement all inter-neuron communication via off-chip address-events. In this work, a new architecture is proposed to overcome these challenges by combining innovations in computation, memory, and communication, respectively, to leverage (a) robust digital neuron circuits; (b) novel transposable SRAM arrays that share learning circuits, which grow only with the number of neurons; and (c) crossbar fan-out for efficient on-chip inter-neuron communication. Through tight integration of memory (synapses) and computation (neurons), a highly configurable chip comprising 256 neurons and 64K binary synapses with on-chip learning based on spike-timing dependent plasticity is demonstrated in 45nm SOI-CMOS. Near-threshold, event-driven operation at 0.53V is demonstrated to maximize power efficiency for real-time pattern classification, recognition, and associative memory tasks. Future scalable systems built from the foundation provided by this work will open up possibilities for ubiquitous ultra-dense, ultra-low power brain-like cognitive computers.",
author = "Jae-sun Seo and Bernard Brezzo and Yong Liu and Parker, {Benjamin D.} and Esser, {Steven K.} and Montoye, {Robert K.} and Bipin Rajendran and Tierno, {Jos{\'e} A.} and Leland Chang and Modha, {Dharmendra S.} and Friedman, {Daniel J.}",
year = "2011",
doi = "10.1109/CICC.2011.6055293",
language = "English (US)",
isbn = "9781457702228",
booktitle = "Proceedings of the Custom Integrated Circuits Conference",

}

TY - GEN

T1 - A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

AU - Seo, Jae-sun

AU - Brezzo, Bernard

AU - Liu, Yong

AU - Parker, Benjamin D.

AU - Esser, Steven K.

AU - Montoye, Robert K.

AU - Rajendran, Bipin

AU - Tierno, José A.

AU - Chang, Leland

AU - Modha, Dharmendra S.

AU - Friedman, Daniel J.

PY - 2011

Y1 - 2011

N2 - Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of analog neuron circuits; (b) the enormous area overhead of learning circuits, which grows with the number of synapses; and (c) the need to implement all inter-neuron communication via off-chip address-events. In this work, a new architecture is proposed to overcome these challenges by combining innovations in computation, memory, and communication, respectively, to leverage (a) robust digital neuron circuits; (b) novel transposable SRAM arrays that share learning circuits, which grow only with the number of neurons; and (c) crossbar fan-out for efficient on-chip inter-neuron communication. Through tight integration of memory (synapses) and computation (neurons), a highly configurable chip comprising 256 neurons and 64K binary synapses with on-chip learning based on spike-timing dependent plasticity is demonstrated in 45nm SOI-CMOS. Near-threshold, event-driven operation at 0.53V is demonstrated to maximize power efficiency for real-time pattern classification, recognition, and associative memory tasks. Future scalable systems built from the foundation provided by this work will open up possibilities for ubiquitous ultra-dense, ultra-low power brain-like cognitive computers.

AB - Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of analog neuron circuits; (b) the enormous area overhead of learning circuits, which grows with the number of synapses; and (c) the need to implement all inter-neuron communication via off-chip address-events. In this work, a new architecture is proposed to overcome these challenges by combining innovations in computation, memory, and communication, respectively, to leverage (a) robust digital neuron circuits; (b) novel transposable SRAM arrays that share learning circuits, which grow only with the number of neurons; and (c) crossbar fan-out for efficient on-chip inter-neuron communication. Through tight integration of memory (synapses) and computation (neurons), a highly configurable chip comprising 256 neurons and 64K binary synapses with on-chip learning based on spike-timing dependent plasticity is demonstrated in 45nm SOI-CMOS. Near-threshold, event-driven operation at 0.53V is demonstrated to maximize power efficiency for real-time pattern classification, recognition, and associative memory tasks. Future scalable systems built from the foundation provided by this work will open up possibilities for ubiquitous ultra-dense, ultra-low power brain-like cognitive computers.

UR - http://www.scopus.com/inward/record.url?scp=80455156136&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80455156136&partnerID=8YFLogxK

U2 - 10.1109/CICC.2011.6055293

DO - 10.1109/CICC.2011.6055293

M3 - Conference contribution

AN - SCOPUS:80455156136

SN - 9781457702228

BT - Proceedings of the Custom Integrated Circuits Conference

ER -