A 3GHz wideband ΣΔ fractional-N synthesizer with voltage-mode exponential CP-PFD

Hiva Hedayati, Bertan Bakkaloglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

A 3GHz wideband ΣΔ fractional-N synthesizer with an exponential settling voltage-mode PFD is presented. The 1MHz band-width Type-I PLL loop utilizes the exponential small-signal settling characteristics of a voltage-mode NMOS (follower) LDO based PFD-CP to reduce in-band quantization noise leakage by more than 13dB without the need for a noise suppression DAC. The PLL is fabricated on a 0.18μm CMOS process with less than 20-mA current consumption from 1.8-V power supply. The measured in-band phase noise at 100 kHz is -107dBc/Hz and out-of-band phase noise at 3 MHz is -130dBc/Hz. The PLL loop settling time for an accuracy of 0.1ppm and a frequency step of 45 MHz is less than 10μs.

Original languageEnglish (US)
Title of host publicationProceedings of the 2009 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2009
Pages325-328
Number of pages4
DOIs
StatePublished - 2009
Event2009 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2009 - Boston, MA, United States
Duration: Jun 7 2009Jun 9 2009

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)1529-2517

Other

Other2009 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2009
Country/TerritoryUnited States
CityBoston, MA
Period6/7/096/9/09

Keywords

  • Fractional-N frequency synthesizers
  • Phase noise
  • Quantization noise
  • Sigma-delta modulation

ASJC Scopus subject areas

  • General Engineering

Fingerprint

Dive into the research topics of 'A 3GHz wideband ΣΔ fractional-N synthesizer with voltage-mode exponential CP-PFD'. Together they form a unique fingerprint.

Cite this