Abstract

Designing high linearity phase-frequency-detectors (PFDs) in low-voltage, deep submicrometer processes is a challenging problem. Nonlinear PFDs can fold out of band phase noise, and increase in-band phase noise of fractional-N PLLs in deep submicron processes. A 3-GHz Type-I Σ Δ fractional-N PLL with an exponentially settling voltage-mode switched-RC phase frequency detector (PFD) is presented. A voltage-mode, fully settled switched-RC (SRC)-based sample-and-hold PFD, providing benefits of both an RC loop-filter and a zero-order hold ( ) suppressing reference clock leakage is presented. The exponentially settled SRC PFD is shown to reduce the in-band leakage of quantization noise by 13 dB in comparison to a similar current-mode charge pump PFD, enabling a measured loop-bandwidth of 890-kHz. The fractional-N PLL is fabricated in a 180-nm CMOS technology with 6 metal layers and consumes 18-mA from a 1.8-V power supply. The worst-case near-integer in-band spur is measured at -62 dBc. The measured in-band phase noise at 100-kHz offset from the 3-GHz carrier is -107 dBc/Hz and out-of-band phase noise at 3-MHz offset is -130 dBc/Hz. The phase-locked loop settling time for a frequency step of 45-MHz and 0.1-ppm accuracy is less than 10-μs.

Original languageEnglish (US)
Article number5976425
Pages (from-to)1681-1690
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number9
DOIs
StatePublished - 2012

Fingerprint

Phase locked loops
Phase noise
Detectors
Electric potential
Clocks
Pumps
Bandwidth
Metals

Keywords

  • Σ Δ fractional-N synthesizer
  • phase-locked loop (PLL)
  • quantization noise

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

Cite this

A 3 GHz wideband Σ Δ fractional-N synthesizer with switched-RC sample-and-hold PFD. / Hedayati, H.; Bakkaloglu, Bertan.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 9, 5976425, 2012, p. 1681-1690.

Research output: Contribution to journalArticle

@article{92bfc820afe349219b8bca73af2ad55c,
title = "A 3 GHz wideband Σ Δ fractional-N synthesizer with switched-RC sample-and-hold PFD",
abstract = "Designing high linearity phase-frequency-detectors (PFDs) in low-voltage, deep submicrometer processes is a challenging problem. Nonlinear PFDs can fold out of band phase noise, and increase in-band phase noise of fractional-N PLLs in deep submicron processes. A 3-GHz Type-I Σ Δ fractional-N PLL with an exponentially settling voltage-mode switched-RC phase frequency detector (PFD) is presented. A voltage-mode, fully settled switched-RC (SRC)-based sample-and-hold PFD, providing benefits of both an RC loop-filter and a zero-order hold ( ) suppressing reference clock leakage is presented. The exponentially settled SRC PFD is shown to reduce the in-band leakage of quantization noise by 13 dB in comparison to a similar current-mode charge pump PFD, enabling a measured loop-bandwidth of 890-kHz. The fractional-N PLL is fabricated in a 180-nm CMOS technology with 6 metal layers and consumes 18-mA from a 1.8-V power supply. The worst-case near-integer in-band spur is measured at -62 dBc. The measured in-band phase noise at 100-kHz offset from the 3-GHz carrier is -107 dBc/Hz and out-of-band phase noise at 3-MHz offset is -130 dBc/Hz. The phase-locked loop settling time for a frequency step of 45-MHz and 0.1-ppm accuracy is less than 10-μs.",
keywords = "Σ Δ fractional-N synthesizer, phase-locked loop (PLL), quantization noise",
author = "H. Hedayati and Bertan Bakkaloglu",
year = "2012",
doi = "10.1109/TVLSI.2011.2161500",
language = "English (US)",
volume = "20",
pages = "1681--1690",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "9",

}

TY - JOUR

T1 - A 3 GHz wideband Σ Δ fractional-N synthesizer with switched-RC sample-and-hold PFD

AU - Hedayati, H.

AU - Bakkaloglu, Bertan

PY - 2012

Y1 - 2012

N2 - Designing high linearity phase-frequency-detectors (PFDs) in low-voltage, deep submicrometer processes is a challenging problem. Nonlinear PFDs can fold out of band phase noise, and increase in-band phase noise of fractional-N PLLs in deep submicron processes. A 3-GHz Type-I Σ Δ fractional-N PLL with an exponentially settling voltage-mode switched-RC phase frequency detector (PFD) is presented. A voltage-mode, fully settled switched-RC (SRC)-based sample-and-hold PFD, providing benefits of both an RC loop-filter and a zero-order hold ( ) suppressing reference clock leakage is presented. The exponentially settled SRC PFD is shown to reduce the in-band leakage of quantization noise by 13 dB in comparison to a similar current-mode charge pump PFD, enabling a measured loop-bandwidth of 890-kHz. The fractional-N PLL is fabricated in a 180-nm CMOS technology with 6 metal layers and consumes 18-mA from a 1.8-V power supply. The worst-case near-integer in-band spur is measured at -62 dBc. The measured in-band phase noise at 100-kHz offset from the 3-GHz carrier is -107 dBc/Hz and out-of-band phase noise at 3-MHz offset is -130 dBc/Hz. The phase-locked loop settling time for a frequency step of 45-MHz and 0.1-ppm accuracy is less than 10-μs.

AB - Designing high linearity phase-frequency-detectors (PFDs) in low-voltage, deep submicrometer processes is a challenging problem. Nonlinear PFDs can fold out of band phase noise, and increase in-band phase noise of fractional-N PLLs in deep submicron processes. A 3-GHz Type-I Σ Δ fractional-N PLL with an exponentially settling voltage-mode switched-RC phase frequency detector (PFD) is presented. A voltage-mode, fully settled switched-RC (SRC)-based sample-and-hold PFD, providing benefits of both an RC loop-filter and a zero-order hold ( ) suppressing reference clock leakage is presented. The exponentially settled SRC PFD is shown to reduce the in-band leakage of quantization noise by 13 dB in comparison to a similar current-mode charge pump PFD, enabling a measured loop-bandwidth of 890-kHz. The fractional-N PLL is fabricated in a 180-nm CMOS technology with 6 metal layers and consumes 18-mA from a 1.8-V power supply. The worst-case near-integer in-band spur is measured at -62 dBc. The measured in-band phase noise at 100-kHz offset from the 3-GHz carrier is -107 dBc/Hz and out-of-band phase noise at 3-MHz offset is -130 dBc/Hz. The phase-locked loop settling time for a frequency step of 45-MHz and 0.1-ppm accuracy is less than 10-μs.

KW - Σ Δ fractional-N synthesizer

KW - phase-locked loop (PLL)

KW - quantization noise

UR - http://www.scopus.com/inward/record.url?scp=84863980876&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84863980876&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2011.2161500

DO - 10.1109/TVLSI.2011.2161500

M3 - Article

AN - SCOPUS:84863980876

VL - 20

SP - 1681

EP - 1690

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 9

M1 - 5976425

ER -