A 2.5mW 80dB DR 36dB SNDR 22MS/s logarithmic pipeline ADC

Jongwoo Lee, Sunghyun Park, Joshua Kang, Jae Sun Seo, Jens Anders, Michael Flynn

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

A switched-capacitor logarithmic pipeline ADC scheme that does not require squaring or any other complex analog functions is described. This approach is ideal where a high dynamic range, but not a high peak SNDR, is required. A signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is implemented in 0.18μm CMOS. The 22MS/s ADC achieves B measured DR of 80dB and a measured SNDR of 36dB, occupies 0.56mm2, and consumes 2.54mW from a 162V supply. The measured dynamic range figure of merit is 174dB.

Original languageEnglish (US)
Title of host publication2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages194-195
Number of pages2
DOIs
StatePublished - Dec 1 2007
Externally publishedYes
Event2007 Symposium on VLSI Circuits, VLSIC - Kyoto, Japan
Duration: Jun 14 2007Jun 16 2007

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2007 Symposium on VLSI Circuits, VLSIC
CountryJapan
CityKyoto
Period6/14/076/16/07

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Keywords

  • Compander and pipeline ADC
  • Logarithmic ADC

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Lee, J., Park, S., Kang, J., Seo, J. S., Anders, J., & Flynn, M. (2007). A 2.5mW 80dB DR 36dB SNDR 22MS/s logarithmic pipeline ADC. In 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers (pp. 194-195). [4342711] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2007.4342711