A 2.5mW 80dB DR 36dB SNDR 22MS/s logarithmic pipeline ADC

Jongwoo Lee, Sunghyun Park, Joshua Kang, Jae-sun Seo, Jens Anders, Michael Flynn

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

A switched-capacitor logarithmic pipeline ADC scheme that does not require squaring or any other complex analog functions is described. This approach is ideal where a high dynamic range, but not a high peak SNDR, is required. A signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is implemented in 0.18μm CMOS. The 22MS/s ADC achieves B measured DR of 80dB and a measured SNDR of 36dB, occupies 0.56mm2, and consumes 2.54mW from a 162V supply. The measured dynamic range figure of merit is 174dB.

Original languageEnglish (US)
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages194-195
Number of pages2
DOIs
StatePublished - 2007
Externally publishedYes
Event2007 Symposium on VLSI Circuits, VLSIC - Kyoto, Japan
Duration: Jun 14 2007Jun 16 2007

Other

Other2007 Symposium on VLSI Circuits, VLSIC
CountryJapan
CityKyoto
Period6/14/076/16/07

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Pipelines
Capacitors

Keywords

  • Compander and pipeline ADC
  • Logarithmic ADC

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Lee, J., Park, S., Kang, J., Seo, J., Anders, J., & Flynn, M. (2007). A 2.5mW 80dB DR 36dB SNDR 22MS/s logarithmic pipeline ADC. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 194-195). [4342711] https://doi.org/10.1109/VLSIC.2007.4342711

A 2.5mW 80dB DR 36dB SNDR 22MS/s logarithmic pipeline ADC. / Lee, Jongwoo; Park, Sunghyun; Kang, Joshua; Seo, Jae-sun; Anders, Jens; Flynn, Michael.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2007. p. 194-195 4342711.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lee, J, Park, S, Kang, J, Seo, J, Anders, J & Flynn, M 2007, A 2.5mW 80dB DR 36dB SNDR 22MS/s logarithmic pipeline ADC. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 4342711, pp. 194-195, 2007 Symposium on VLSI Circuits, VLSIC, Kyoto, Japan, 6/14/07. https://doi.org/10.1109/VLSIC.2007.4342711
Lee J, Park S, Kang J, Seo J, Anders J, Flynn M. A 2.5mW 80dB DR 36dB SNDR 22MS/s logarithmic pipeline ADC. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2007. p. 194-195. 4342711 https://doi.org/10.1109/VLSIC.2007.4342711
Lee, Jongwoo ; Park, Sunghyun ; Kang, Joshua ; Seo, Jae-sun ; Anders, Jens ; Flynn, Michael. / A 2.5mW 80dB DR 36dB SNDR 22MS/s logarithmic pipeline ADC. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2007. pp. 194-195
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