A 2.5mW 80dB DR 36dB SNDR 22MS/s logarithmic pipeline ADC

Jongwoo Lee; Sunghyun Park; Joshua Kang; Jae Sun Seo; Jens Anders; Michael Flynn

doi:10.1109/VLSIC.2007.4342711

A 2.5mW 80dB DR 36dB SNDR 22MS/s logarithmic pipeline ADC

Jongwoo Lee, Sunghyun Park, Joshua Kang, Jae Sun Seo, Jens Anders, Michael Flynn

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Scopus citations

Abstract

A switched-capacitor logarithmic pipeline ADC scheme that does not require squaring or any other complex analog functions is described. This approach is ideal where a high dynamic range, but not a high peak SNDR, is required. A signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is implemented in 0.18μm CMOS. The 22MS/s ADC achieves B measured DR of 80dB and a measured SNDR of 36dB, occupies 0.56mm², and consumes 2.54mW from a 162V supply. The measured dynamic range figure of merit is 174dB.

Original language	English (US)
Title of host publication	2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages	194-195
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2007.4342711
State	Published - 2007
Externally published	Yes
Event	2007 Symposium on VLSI Circuits, VLSIC - Kyoto, Japan Duration: Jun 14 2007 → Jun 16 2007

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2007 Symposium on VLSI Circuits, VLSIC
Country/Territory	Japan
City	Kyoto
Period	6/14/07 → 6/16/07

Keywords

Compander and pipeline ADC
Logarithmic ADC

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/VLSIC.2007.4342711

Cite this

Lee, J, Park, S, Kang, J, Seo, JS, Anders, J & Flynn, M 2007, A 2.5mW 80dB DR 36dB SNDR 22MS/s logarithmic pipeline ADC. in 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers., 4342711, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 194-195, 2007 Symposium on VLSI Circuits, VLSIC, Kyoto, Japan, 6/14/07. https://doi.org/10.1109/VLSIC.2007.4342711

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title = "A 2.5mW 80dB DR 36dB SNDR 22MS/s logarithmic pipeline ADC",

abstract = "A switched-capacitor logarithmic pipeline ADC scheme that does not require squaring or any other complex analog functions is described. This approach is ideal where a high dynamic range, but not a high peak SNDR, is required. A signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is implemented in 0.18μm CMOS. The 22MS/s ADC achieves B measured DR of 80dB and a measured SNDR of 36dB, occupies 0.56mm2, and consumes 2.54mW from a 162V supply. The measured dynamic range figure of merit is 174dB.",

keywords = "Compander and pipeline ADC, Logarithmic ADC",

author = "Jongwoo Lee and Sunghyun Park and Joshua Kang and Seo, {Jae Sun} and Jens Anders and Michael Flynn",

year = "2007",

doi = "10.1109/VLSIC.2007.4342711",

language = "English (US)",

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series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "194--195",

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note = "2007 Symposium on VLSI Circuits, VLSIC ; Conference date: 14-06-2007 Through 16-06-2007",

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T1 - A 2.5mW 80dB DR 36dB SNDR 22MS/s logarithmic pipeline ADC

AU - Lee, Jongwoo

AU - Park, Sunghyun

AU - Kang, Joshua

AU - Seo, Jae Sun

AU - Anders, Jens

AU - Flynn, Michael

PY - 2007

Y1 - 2007

N2 - A switched-capacitor logarithmic pipeline ADC scheme that does not require squaring or any other complex analog functions is described. This approach is ideal where a high dynamic range, but not a high peak SNDR, is required. A signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is implemented in 0.18μm CMOS. The 22MS/s ADC achieves B measured DR of 80dB and a measured SNDR of 36dB, occupies 0.56mm2, and consumes 2.54mW from a 162V supply. The measured dynamic range figure of merit is 174dB.

AB - A switched-capacitor logarithmic pipeline ADC scheme that does not require squaring or any other complex analog functions is described. This approach is ideal where a high dynamic range, but not a high peak SNDR, is required. A signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is implemented in 0.18μm CMOS. The 22MS/s ADC achieves B measured DR of 80dB and a measured SNDR of 36dB, occupies 0.56mm2, and consumes 2.54mW from a 162V supply. The measured dynamic range figure of merit is 174dB.

KW - Compander and pipeline ADC

KW - Logarithmic ADC

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DO - 10.1109/VLSIC.2007.4342711

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T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

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BT - 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers

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Y2 - 14 June 2007 through 16 June 2007

ER -

A 2.5mW 80dB DR 36dB SNDR 22MS/s logarithmic pipeline ADC

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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