A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC

Jongwoo Lee, Joshua Kang, Sunghyun Park, Jae-sun Seo, Jens Anders, Jorge Guilherme, Michael P. Flynn

Research output: Contribution to journalArticle

23 Citations (Scopus)

Abstract

A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 μm CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.

Original languageEnglish (US)
Article number18
Pages (from-to)2755-2765
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number10
DOIs
StatePublished - Oct 2009
Externally publishedYes

Fingerprint

Digital to analog conversion
Pipelines
Capacitors

Keywords

  • Compander
  • Logarithmic ADC
  • Pipeline ADC

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Lee, J., Kang, J., Park, S., Seo, J., Anders, J., Guilherme, J., & Flynn, M. P. (2009). A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC. IEEE Journal of Solid-State Circuits, 44(10), 2755-2765. [18]. https://doi.org/10.1109/JSSC.2009.2028052

A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC. / Lee, Jongwoo; Kang, Joshua; Park, Sunghyun; Seo, Jae-sun; Anders, Jens; Guilherme, Jorge; Flynn, Michael P.

In: IEEE Journal of Solid-State Circuits, Vol. 44, No. 10, 18, 10.2009, p. 2755-2765.

Research output: Contribution to journalArticle

Lee, J, Kang, J, Park, S, Seo, J, Anders, J, Guilherme, J & Flynn, MP 2009, 'A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC', IEEE Journal of Solid-State Circuits, vol. 44, no. 10, 18, pp. 2755-2765. https://doi.org/10.1109/JSSC.2009.2028052
Lee, Jongwoo ; Kang, Joshua ; Park, Sunghyun ; Seo, Jae-sun ; Anders, Jens ; Guilherme, Jorge ; Flynn, Michael P. / A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC. In: IEEE Journal of Solid-State Circuits. 2009 ; Vol. 44, No. 10. pp. 2755-2765.
@article{fa79dac7d2464b84af0e24a1ed4c2604,
title = "A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC",
abstract = "A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 μm CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.",
keywords = "Compander, Logarithmic ADC, Pipeline ADC",
author = "Jongwoo Lee and Joshua Kang and Sunghyun Park and Jae-sun Seo and Jens Anders and Jorge Guilherme and Flynn, {Michael P.}",
year = "2009",
month = "10",
doi = "10.1109/JSSC.2009.2028052",
language = "English (US)",
volume = "44",
pages = "2755--2765",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "10",

}

TY - JOUR

T1 - A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC

AU - Lee, Jongwoo

AU - Kang, Joshua

AU - Park, Sunghyun

AU - Seo, Jae-sun

AU - Anders, Jens

AU - Guilherme, Jorge

AU - Flynn, Michael P.

PY - 2009/10

Y1 - 2009/10

N2 - A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 μm CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.

AB - A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 μm CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.

KW - Compander

KW - Logarithmic ADC

KW - Pipeline ADC

UR - http://www.scopus.com/inward/record.url?scp=70350578839&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70350578839&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2009.2028052

DO - 10.1109/JSSC.2009.2028052

M3 - Article

VL - 44

SP - 2755

EP - 2765

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 10

M1 - 18

ER -