A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC

Jongwoo Lee, Joshua Kang, Sunghyun Park, Jae Sun Seo, Jens Anders, Jorge Guilherme, Michael P. Flynn

Research output: Contribution to journalArticle

25 Scopus citations

Abstract

A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 μm CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.

Original languageEnglish (US)
Article number18
Pages (from-to)2755-2765
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number10
DOIs
StatePublished - Oct 1 2009

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Keywords

  • Compander
  • Logarithmic ADC
  • Pipeline ADC

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Lee, J., Kang, J., Park, S., Seo, J. S., Anders, J., Guilherme, J., & Flynn, M. P. (2009). A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC. IEEE Journal of Solid-State Circuits, 44(10), 2755-2765. [18]. https://doi.org/10.1109/JSSC.2009.2028052