A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction

Yanlong Zhang, Arindam Sanyal, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, Nan Sun

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

This paper presents a highly digital technique that can significantly reduce the quantization noise of fractional-N phase-locked loops (PLLs) at all frequencies. This is achieved by using an array of dividers to realize spatial averaging. A fractional Δ Σ modulator (DSM) and a data-weighted averaging (DWA) module are used to generate the vector division ratio for the divider array. Based on this technique, a 2.4-GHz fractional-N frequency synthesizer is implemented in 40 nm CMOS process, in which spatial averaging is achieved with only one divider and phase selection to lower the power. Measurement results show that the phase noise at 1 MHz and 10 MHz frequency offsets are improved by 8 dB and 20 dB, respectively, compared to the conventional architecture. The output root-mean-square (rms) jitter is reduced from 10.4 ps to 3.1 ps, same as that at integer mode. The proposed synthesizer consumes only 4.9 mW in total, leading to a FoM of-223.3 dB.

Original languageEnglish (US)
Title of host publication2019 IEEE Custom Integrated Circuits Conference, CICC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538693957
DOIs
StatePublished - Apr 2019
Externally publishedYes
Event40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019 - Austin, United States
Duration: Apr 14 2019Apr 17 2019

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2019-April
ISSN (Print)0886-5930

Conference

Conference40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019
Country/TerritoryUnited States
CityAustin
Period4/14/194/17/19

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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