This paper presents a highly digital technique that can significantly reduce the quantization noise of fractional-N phase-locked loops (PLLs) at all frequencies. This is achieved by using an array of dividers to realize spatial averaging. A fractional Δ Σ modulator (DSM) and a data-weighted averaging (DWA) module are used to generate the vector division ratio for the divider array. Based on this technique, a 2.4-GHz fractional-N frequency synthesizer is implemented in 40 nm CMOS process, in which spatial averaging is achieved with only one divider and phase selection to lower the power. Measurement results show that the phase noise at 1 MHz and 10 MHz frequency offsets are improved by 8 dB and 20 dB, respectively, compared to the conventional architecture. The output root-mean-square (rms) jitter is reduced from 10.4 ps to 3.1 ps, same as that at integer mode. The proposed synthesizer consumes only 4.9 mW in total, leading to a FoM of-223.3 dB.