TY - GEN
T1 - A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction
AU - Zhang, Yanlong
AU - Sanyal, Arindam
AU - Quan, Xing
AU - Wen, Kailin
AU - Tang, Xiyuan
AU - Jin, Gang
AU - Geng, Li
AU - Sun, Nan
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/4
Y1 - 2019/4
N2 - This paper presents a highly digital technique that can significantly reduce the quantization noise of fractional-N phase-locked loops (PLLs) at all frequencies. This is achieved by using an array of dividers to realize spatial averaging. A fractional Δ Σ modulator (DSM) and a data-weighted averaging (DWA) module are used to generate the vector division ratio for the divider array. Based on this technique, a 2.4-GHz fractional-N frequency synthesizer is implemented in 40 nm CMOS process, in which spatial averaging is achieved with only one divider and phase selection to lower the power. Measurement results show that the phase noise at 1 MHz and 10 MHz frequency offsets are improved by 8 dB and 20 dB, respectively, compared to the conventional architecture. The output root-mean-square (rms) jitter is reduced from 10.4 ps to 3.1 ps, same as that at integer mode. The proposed synthesizer consumes only 4.9 mW in total, leading to a FoM of-223.3 dB.
AB - This paper presents a highly digital technique that can significantly reduce the quantization noise of fractional-N phase-locked loops (PLLs) at all frequencies. This is achieved by using an array of dividers to realize spatial averaging. A fractional Δ Σ modulator (DSM) and a data-weighted averaging (DWA) module are used to generate the vector division ratio for the divider array. Based on this technique, a 2.4-GHz fractional-N frequency synthesizer is implemented in 40 nm CMOS process, in which spatial averaging is achieved with only one divider and phase selection to lower the power. Measurement results show that the phase noise at 1 MHz and 10 MHz frequency offsets are improved by 8 dB and 20 dB, respectively, compared to the conventional architecture. The output root-mean-square (rms) jitter is reduced from 10.4 ps to 3.1 ps, same as that at integer mode. The proposed synthesizer consumes only 4.9 mW in total, leading to a FoM of-223.3 dB.
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U2 - 10.1109/CICC.2019.8780206
DO - 10.1109/CICC.2019.8780206
M3 - Conference contribution
AN - SCOPUS:85070538835
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - 2019 IEEE Custom Integrated Circuits Conference, CICC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019
Y2 - 14 April 2019 through 17 April 2019
ER -