A 24-μW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique

Long Chen; Arindam Sanyal; Ji Ma; Nan Sun

doi:10.1109/ESSCIRC.2014.6942061

A 24-μW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique

Long Chen, Arindam Sanyal, Ji Ma, Nan Sun

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

69 Scopus citations

Abstract

This paper presents a low-power SAR ADC with a bidirectional single-side (BSS) switching technique. It reduces the DAC reference power and the total number of unit capacitors by 86% and 75% respectively, compared to the conventional SAR switching technique. It also minimizes the DAC switch driving power as it has only 1 single-side switching event every comparison cycle. Unlike the existing monotonic switching technique that also has only 1 switching event, the comparator input common-mode voltage for the proposed technique does not converge to ground but to V_cm, and thus, obviates the need for a specially designed comparator. To further reduce power, a segmented common-centroid capacitor layout is developed to ensure good matching accuracy. An 11-bit prototype ADC fabricated in 0.18-μm 1P6M CMOS technology achieves an ENOB of 10.3 bits and an SFDR of 77 dB. Operating at 1 MS/s, it consumes only 24 μW from a 1V power supply, leading to a FOM of 19.9 fJ/conv-step.

Original language	English (US)
Title of host publication	ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference
Editors	Pietro Andreani, Andrea Bevilacqua, Gaudenzio Meneghesso
Publisher	IEEE Computer Society
Pages	219-222
Number of pages	4
ISBN (Electronic)	9781479956944
DOIs	https://doi.org/10.1109/ESSCIRC.2014.6942061
State	Published - Oct 31 2014
Externally published	Yes
Event	40th European Solid-State Circuit Conference, ESSCIRC 2014 - Venezia Lido, Italy Duration: Sep 22 2014 → Sep 26 2014

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	40th European Solid-State Circuit Conference, ESSCIRC 2014
Country/Territory	Italy
City	Venezia Lido
Period	9/22/14 → 9/26/14

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ESSCIRC.2014.6942061

Cite this

Chen, L., Sanyal, A., Ma, J., & Sun, N. (2014). A 24-μW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique. In P. Andreani, A. Bevilacqua, & G. Meneghesso (Eds.), ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference (pp. 219-222). Article 6942061 (European Solid-State Circuits Conference). IEEE Computer Society. https://doi.org/10.1109/ESSCIRC.2014.6942061

A 24-μW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique. / Chen, Long; Sanyal, Arindam; Ma, Ji et al.
ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. ed. / Pietro Andreani; Andrea Bevilacqua; Gaudenzio Meneghesso. IEEE Computer Society, 2014. p. 219-222 6942061 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chen, L, Sanyal, A, Ma, J & Sun, N 2014, A 24-μW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique. in P Andreani, A Bevilacqua & G Meneghesso (eds), ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference., 6942061, European Solid-State Circuits Conference, IEEE Computer Society, pp. 219-222, 40th European Solid-State Circuit Conference, ESSCIRC 2014, Venezia Lido, Italy, 9/22/14. https://doi.org/10.1109/ESSCIRC.2014.6942061

Chen L, Sanyal A, Ma J, Sun N. A 24-μW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique. In Andreani P, Bevilacqua A, Meneghesso G, editors, ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. IEEE Computer Society. 2014. p. 219-222. 6942061. (European Solid-State Circuits Conference). doi: 10.1109/ESSCIRC.2014.6942061

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abstract = "This paper presents a low-power SAR ADC with a bidirectional single-side (BSS) switching technique. It reduces the DAC reference power and the total number of unit capacitors by 86% and 75% respectively, compared to the conventional SAR switching technique. It also minimizes the DAC switch driving power as it has only 1 single-side switching event every comparison cycle. Unlike the existing monotonic switching technique that also has only 1 switching event, the comparator input common-mode voltage for the proposed technique does not converge to ground but to Vcm, and thus, obviates the need for a specially designed comparator. To further reduce power, a segmented common-centroid capacitor layout is developed to ensure good matching accuracy. An 11-bit prototype ADC fabricated in 0.18-μm 1P6M CMOS technology achieves an ENOB of 10.3 bits and an SFDR of 77 dB. Operating at 1 MS/s, it consumes only 24 μW from a 1V power supply, leading to a FOM of 19.9 fJ/conv-step.",

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N2 - This paper presents a low-power SAR ADC with a bidirectional single-side (BSS) switching technique. It reduces the DAC reference power and the total number of unit capacitors by 86% and 75% respectively, compared to the conventional SAR switching technique. It also minimizes the DAC switch driving power as it has only 1 single-side switching event every comparison cycle. Unlike the existing monotonic switching technique that also has only 1 switching event, the comparator input common-mode voltage for the proposed technique does not converge to ground but to Vcm, and thus, obviates the need for a specially designed comparator. To further reduce power, a segmented common-centroid capacitor layout is developed to ensure good matching accuracy. An 11-bit prototype ADC fabricated in 0.18-μm 1P6M CMOS technology achieves an ENOB of 10.3 bits and an SFDR of 77 dB. Operating at 1 MS/s, it consumes only 24 μW from a 1V power supply, leading to a FOM of 19.9 fJ/conv-step.

AB - This paper presents a low-power SAR ADC with a bidirectional single-side (BSS) switching technique. It reduces the DAC reference power and the total number of unit capacitors by 86% and 75% respectively, compared to the conventional SAR switching technique. It also minimizes the DAC switch driving power as it has only 1 single-side switching event every comparison cycle. Unlike the existing monotonic switching technique that also has only 1 switching event, the comparator input common-mode voltage for the proposed technique does not converge to ground but to Vcm, and thus, obviates the need for a specially designed comparator. To further reduce power, a segmented common-centroid capacitor layout is developed to ensure good matching accuracy. An 11-bit prototype ADC fabricated in 0.18-μm 1P6M CMOS technology achieves an ENOB of 10.3 bits and an SFDR of 77 dB. Operating at 1 MS/s, it consumes only 24 μW from a 1V power supply, leading to a FOM of 19.9 fJ/conv-step.

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A 24-μW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique

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