A 20-MS/s to 40-MS/s reconfigurable pipeline ADC implemented with parallel OTA scaling

Kailash Chandrashekar, Marco Corsi, John Fattaruso, Bertan Bakkaloglu

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

A reconfigurable 12-b pipeline analog-to-digital converter (ADC) implemented by enabling or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying the dc bias conditions of critical analog nodes, reducing design complexity, and allowing an existing design to be rapidly reconfigured for new specifications. The ADC can be designed for optimal power consumption over the entire sampling rate range due to the linear power scaling provided by the parallel OTA approach. The proposed ADC operates over a sampling rate range of 20 MS/s to 40 MS/s with > 62 dB SNDR. The analog power varies linearly from 36 mW at 20 MS/s to 72 mW at 40 MS/s. The ADC was fabricated in 0.18-μ CMOS process and occupies a die area of 1.9μ2.

Original languageEnglish (US)
Article number5550467
Pages (from-to)602-606
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume57
Issue number8
DOIs
StatePublished - Aug 2010

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Digital to analog conversion
Pipelines
Sampling
Electric power utilization
Specifications

Keywords

  • Analog-to-digital converter
  • parallel OTA
  • power scalable
  • reconfigurable

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 20-MS/s to 40-MS/s reconfigurable pipeline ADC implemented with parallel OTA scaling. / Chandrashekar, Kailash; Corsi, Marco; Fattaruso, John; Bakkaloglu, Bertan.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 57, No. 8, 5550467, 08.2010, p. 602-606.

Research output: Contribution to journalArticle

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