A 18.5-fJ/step VCO-based 0-1 MASH ΔΣ ADC with digital background calibration

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Scopus citations

Abstract

A scaling-friendly and energy-efficient 0-1 MASH ΔΣ ADC is proposed in this work. An 8b SAR is used as the 1st stage for coarse quantization. A ring VCO is used as the 2nd stage for fine quantization. The proposed ADC uses digital background calibration to track VCO gain variation across PVT. A 40nm CMOS prototype achieves a Walden FoM of 18.5 fJ/conv-step while operating from 1.1V supply.

Original languageEnglish (US)
Title of host publication2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509006342
DOIs
StatePublished - Sep 21 2016
Externally publishedYes
Event30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States
Duration: Jun 14 2016Jun 17 2016

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2016-September

Conference

Conference30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Country/TerritoryUnited States
CityHonolulu
Period6/14/166/17/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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