A 18.5-fJ/step VCO-based 0-1 MASH ΔΣ ADC with digital background calibration

Arindam Sanyal; Nan Sun

doi:10.1109/VLSIC.2016.7573465

A 18.5-fJ/step VCO-based 0-1 MASH ΔΣ ADC with digital background calibration

Arindam Sanyal, Nan Sun

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

31 Scopus citations

Abstract

A scaling-friendly and energy-efficient 0-1 MASH ΔΣ ADC is proposed in this work. An 8b SAR is used as the 1st stage for coarse quantization. A ring VCO is used as the 2nd stage for fine quantization. The proposed ADC uses digital background calibration to track VCO gain variation across PVT. A 40nm CMOS prototype achieves a Walden FoM of 18.5 fJ/conv-step while operating from 1.1V supply.

Original language	English (US)
Title of host publication	2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509006342
DOIs	https://doi.org/10.1109/VLSIC.2016.7573465
State	Published - Sep 21 2016
Externally published	Yes
Event	30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States Duration: Jun 14 2016 → Jun 17 2016

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2016-September

Conference

Conference	30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Country/Territory	United States
City	Honolulu
Period	6/14/16 → 6/17/16

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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10.1109/VLSIC.2016.7573465

Cite this

A 18.5-fJ/step VCO-based 0-1 MASH ΔΣ ADC with digital background calibration. / Sanyal, Arindam; Sun, Nan.
2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7573465 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2016-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sanyal, A & Sun, N 2016, A 18.5-fJ/step VCO-based 0-1 MASH ΔΣ ADC with digital background calibration. in 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016., 7573465, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2016-September, Institute of Electrical and Electronics Engineers Inc., 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016, Honolulu, United States, 6/14/16. https://doi.org/10.1109/VLSIC.2016.7573465

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A 18.5-fJ/step VCO-based 0-1 MASH ΔΣ ADC with digital background calibration

Abstract

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ASJC Scopus subject areas

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