A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks

Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae Sun Seo, Mingoo Seok

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Capacitor-based in-memory computing (IMC) SRAM has recently gained significant attention as it achieves high energy-efficiency for deep convolutional neural networks (DCNN) and robustness against PVT variations [1], [3], [7], [8]. To further improve energy-efficiency and robustness, we identify two places of bottleneck in prior capacitive IMC works, namely (i) input drivers (or digital-to-analog converters, DACs) which charge and discharge various capacitors, and (ii) analog-to-digital converters (ADCs) which convert analog voltage/current signals into digital values.

Original languageEnglish (US)
Title of host publication2022 IEEE Custom Integrated Circuits Conference, CICC 2022 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665407564
DOIs
StatePublished - 2022
Event43rd Annual IEEE Custom Integrated Circuits Conference, CICC 2022 - Newport Beach, United States
Duration: Apr 24 2022Apr 27 2022

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2022-April
ISSN (Print)0886-5930

Conference

Conference43rd Annual IEEE Custom Integrated Circuits Conference, CICC 2022
Country/TerritoryUnited States
CityNewport Beach
Period4/24/224/27/22

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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