A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks

Bo Zhang; Jyotishman Saikia; Jian Meng; Dewei Wang; Soonwan Kwon; Sungmeen Myung; Hyunsoo Kim; Sang Joon Kim; Jae Sun Seo; Mingoo Seok

doi:10.1109/CICC53496.2022.9772781

A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks

Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae Sun Seo, Mingoo Seok

Engineering, Ira A. Fulton Schools of (IAFSE)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Scopus citations

Abstract

Capacitor-based in-memory computing (IMC) SRAM has recently gained significant attention as it achieves high energy-efficiency for deep convolutional neural networks (DCNN) and robustness against PVT variations [1], [3], [7], [8]. To further improve energy-efficiency and robustness, we identify two places of bottleneck in prior capacitive IMC works, namely (i) input drivers (or digital-to-analog converters, DACs) which charge and discharge various capacitors, and (ii) analog-to-digital converters (ADCs) which convert analog voltage/current signals into digital values.

Original language	English (US)
Title of host publication	2022 IEEE Custom Integrated Circuits Conference, CICC 2022 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665407564
DOIs	https://doi.org/10.1109/CICC53496.2022.9772781
State	Published - 2022
Event	43rd Annual IEEE Custom Integrated Circuits Conference, CICC 2022 - Newport Beach, United States Duration: Apr 24 2022 → Apr 27 2022

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
Volume	2022-April
ISSN (Print)	0886-5930

Conference

Conference	43rd Annual IEEE Custom Integrated Circuits Conference, CICC 2022
Country/Territory	United States
City	Newport Beach
Period	4/24/22 → 4/27/22

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC53496.2022.9772781

Cite this

Zhang, B., Saikia, J., Meng, J., Wang, D., Kwon, S., Myung, S., Kim, H., Kim, S. J., Seo, J. S., & Seok, M. (2022). A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks. In 2022 IEEE Custom Integrated Circuits Conference, CICC 2022 - Proceedings (Proceedings of the Custom Integrated Circuits Conference; Vol. 2022-April). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC53496.2022.9772781

A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks. / Zhang, Bo; Saikia, Jyotishman; Meng, Jian et al.
2022 IEEE Custom Integrated Circuits Conference, CICC 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2022. (Proceedings of the Custom Integrated Circuits Conference; Vol. 2022-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhang, B, Saikia, J, Meng, J, Wang, D, Kwon, S, Myung, S, Kim, H, Kim, SJ, Seo, JS & Seok, M 2022, A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks. in 2022 IEEE Custom Integrated Circuits Conference, CICC 2022 - Proceedings. Proceedings of the Custom Integrated Circuits Conference, vol. 2022-April, Institute of Electrical and Electronics Engineers Inc., 43rd Annual IEEE Custom Integrated Circuits Conference, CICC 2022, Newport Beach, United States, 4/24/22. https://doi.org/10.1109/CICC53496.2022.9772781

Zhang B, Saikia J, Meng J, Wang D, Kwon S, Myung S et al. A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks. In 2022 IEEE Custom Integrated Circuits Conference, CICC 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2022. (Proceedings of the Custom Integrated Circuits Conference). doi: 10.1109/CICC53496.2022.9772781

Zhang, Bo ; Saikia, Jyotishman ; Meng, Jian et al. / A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks. 2022 IEEE Custom Integrated Circuits Conference, CICC 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2022. (Proceedings of the Custom Integrated Circuits Conference).

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title = "A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks",

abstract = "Capacitor-based in-memory computing (IMC) SRAM has recently gained significant attention as it achieves high energy-efficiency for deep convolutional neural networks (DCNN) and robustness against PVT variations [1], [3], [7], [8]. To further improve energy-efficiency and robustness, we identify two places of bottleneck in prior capacitive IMC works, namely (i) input drivers (or digital-to-analog converters, DACs) which charge and discharge various capacitors, and (ii) analog-to-digital converters (ADCs) which convert analog voltage/current signals into digital values.",

author = "Bo Zhang and Jyotishman Saikia and Jian Meng and Dewei Wang and Soonwan Kwon and Sungmeen Myung and Hyunsoo Kim and Kim, {Sang Joon} and Seo, {Jae Sun} and Mingoo Seok",

note = "Funding Information: Acknowledgement: This work is partially supported by Samsung Advanced Institute of Technology and SRC/DARPA JUMP C-BRIC. Publisher Copyright: {\textcopyright} 2022 IEEE.; 43rd Annual IEEE Custom Integrated Circuits Conference, CICC 2022 ; Conference date: 24-04-2022 Through 27-04-2022",

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AU - Saikia, Jyotishman

AU - Meng, Jian

AU - Wang, Dewei

AU - Kwon, Soonwan

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AB - Capacitor-based in-memory computing (IMC) SRAM has recently gained significant attention as it achieves high energy-efficiency for deep convolutional neural networks (DCNN) and robustness against PVT variations [1], [3], [7], [8]. To further improve energy-efficiency and robustness, we identify two places of bottleneck in prior capacitive IMC works, namely (i) input drivers (or digital-to-analog converters, DACs) which charge and discharge various capacitors, and (ii) analog-to-digital converters (ADCs) which convert analog voltage/current signals into digital values.

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A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks

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