A 1.66 mV FOM output cap-less LDO with current-reused dynamic biasing and 20 ns settling time

Chirag Desai, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

A fully integrated output capacitor-less, nMOS regulation FET low-dropout (LDO) regulator with fast transient response for system-on-chip power regulation applications is presented. The error amplifier (EA) consists of a differential cross-coupled common-gate (CG) input stage achieving twice the transconductance and unity-gainbandwidth in comparison to a conventional differential common-source stage. The low input resistance of the CG EA improves stability of the LDO over a wide range of load currents. The LDO employs a currentreused dynamic biasing technique to further improve the load transient response, with no extra quiescent current. It is designed and fabricated in a 0.18-μm CMOS technology for an input voltage range of 1.6-1.8 V, and an output voltage range of 1.4-1.6 V. Measured undershoot is 158 mV and settling time is 20 ns for 9-40 mA load change in 250 ps edge-Time with zero load capacitance. The LDO core consumes 130 μA of quiescent current, occupies 0.21 mm2 die area, and sustains 0-50 pF of on-chip load capacitance.

Original languageEnglish (US)
Article number08309346
Pages (from-to)50-53
Number of pages4
JournalIEEE Solid-State Circuits Letters
Volume1
Issue number2
DOIs
StatePublished - Feb 2018
Externally publishedYes

Keywords

  • Cross-coupled common-gate (CG) input stage
  • Currentreused dynamic biasing
  • Fast transient response
  • High slew rate
  • Lowdropout (LDO) regulator.

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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