A 1.5V 1mA 80dB passive ΣΔ ADC in 0.13μm digital CMOS process

Feng Chen; Srinath Ramaswamy; Bertan Bakkaloglu

A 1.5V 1mA 80dB passive ΣΔ ADC in 0.13μm digital CMOS process

Feng Chen, Srinath Ramaswamy, Bertan Bakkaloglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A passive switched-capacitor ΣΔ ADC consisting of only switches, capacitors and a comparator, is implemented in a 0.13μm digital CMOS process. This high-speed low-voltage architecture is used in a zero-IF GSM transceiver and has a measured peak SNDR of 67dB over a bandwidth of 100kHz with a SFDR of 75dB and a dynamic range of 72dB. The ADC consumes 1mA from a 1.5V power supply at a clock rate of 104MHz.

Original language	English (US)
Title of host publication	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors	L.C. Fujino, A. Grabel, D. Jeager, K.C. Smith
Pages	53-55+477
State	Published - 2003
Externally published	Yes
Event	2003 Digest of Technical Papers - , United States Duration: Feb 9 2003 → Feb 13 2003

Other

Other	2003 Digest of Technical Papers
Country/Territory	United States
Period	2/9/03 → 2/13/03

ASJC Scopus subject areas

Electrical and Electronic Engineering
Hardware and Architecture

Cite this

@inproceedings{1c7e1a8620a245828c74de9ff96a076f,

title = "A 1.5V 1mA 80dB passive ΣΔ ADC in 0.13μm digital CMOS process",

abstract = "A passive switched-capacitor ΣΔ ADC consisting of only switches, capacitors and a comparator, is implemented in a 0.13μm digital CMOS process. This high-speed low-voltage architecture is used in a zero-IF GSM transceiver and has a measured peak SNDR of 67dB over a bandwidth of 100kHz with a SFDR of 75dB and a dynamic range of 72dB. The ADC consumes 1mA from a 1.5V power supply at a clock rate of 104MHz.",

author = "Feng Chen and Srinath Ramaswamy and Bertan Bakkaloglu",

year = "2003",

language = "English (US)",

pages = "53--55+477",

editor = "L.C. Fujino and A. Grabel and D. Jeager and K.C. Smith",

booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

note = "2003 Digest of Technical Papers ; Conference date: 09-02-2003 Through 13-02-2003",

}

TY - GEN

T1 - A 1.5V 1mA 80dB passive ΣΔ ADC in 0.13μm digital CMOS process

AU - Chen, Feng

AU - Ramaswamy, Srinath

AU - Bakkaloglu, Bertan

PY - 2003

Y1 - 2003

N2 - A passive switched-capacitor ΣΔ ADC consisting of only switches, capacitors and a comparator, is implemented in a 0.13μm digital CMOS process. This high-speed low-voltage architecture is used in a zero-IF GSM transceiver and has a measured peak SNDR of 67dB over a bandwidth of 100kHz with a SFDR of 75dB and a dynamic range of 72dB. The ADC consumes 1mA from a 1.5V power supply at a clock rate of 104MHz.

AB - A passive switched-capacitor ΣΔ ADC consisting of only switches, capacitors and a comparator, is implemented in a 0.13μm digital CMOS process. This high-speed low-voltage architecture is used in a zero-IF GSM transceiver and has a measured peak SNDR of 67dB over a bandwidth of 100kHz with a SFDR of 75dB and a dynamic range of 72dB. The ADC consumes 1mA from a 1.5V power supply at a clock rate of 104MHz.

UR - http://www.scopus.com/inward/record.url?scp=0038306658&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0038306658&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0038306658

SP - 53-55+477

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

A2 - Fujino, L.C.

A2 - Grabel, A.

A2 - Jeager, D.

A2 - Smith, K.C.

T2 - 2003 Digest of Technical Papers

Y2 - 9 February 2003 through 13 February 2003

ER -

A 1.5V 1mA 80dB passive ΣΔ ADC in 0.13μm digital CMOS process

Abstract

Other

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this