TY - JOUR
T1 - A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process
AU - Bakkaloglu, Bertan
AU - Fontaine, Paul
AU - Mohieldin, Ahmed Nader
AU - Peng, Solti
AU - Fang, Sher Jiun
AU - Dülger, Fikret
PY - 2006/5
Y1 - 2006/5
N2 - A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm 2.
AB - A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm 2.
KW - CMOS integrated circuits
KW - Low-noise amplifier
KW - Multimode
KW - Radio frequency integrated circuits
KW - Transceivers
KW - Wireless
UR - http://www.scopus.com/inward/record.url?scp=33646411742&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33646411742&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2006.872740
DO - 10.1109/JSSC.2006.872740
M3 - Article
AN - SCOPUS:33646411742
SN - 0018-9200
VL - 41
SP - 1149
EP - 1158
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 5
ER -